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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Features
General
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Extracts and outputs, on a serial link, all transport overhead bytes in the receive data and inserts any, or all, transport overhead bytes in the transmit data using a corresponding serial input. Extracts and outputs, on serial links, the section user channel (F1), orderwire channels (E1, E2), and data communication channels (D1--D3 and D4--D12) for the receive data. Inserts corresponding serial input signals into the transmit data. Extracts, integrates, and stores the automatic protection switch (APS) channel bytes (K1, K2) for the receive data and detects protection switch failure alarms. Inserts APS bytes in the transmit data from internal registers or from add data overhead bytes. Detects line alarm indication signal (AIS) and remote defect indication (RDI) based on the K2 byte of the receive data. Inserts line AIS and RDI in the transmit data. Optionally inserts line RDI automatically due to LOS, LOF, or line AIS defects. Extracts, integrates, and stores the synchronization status byte (S1) for the receive data. Inserts the synchronization status byte into the transmit data from an internal register or from a value encoded on the transmit frame synchronous input. Calculates, detects, and counts section and line BIP-8 errors (B1, B2) for the receive data, and inserts BIP-8 in the transmit data. Supports either bit or block error accumulation of B1 errors (separately provisionable), and bit error accumulation of B2 errors. Extracts and counts line remote errors (REI) for the receive data (M1), and inserts REI in the transmit data based on B2 errors. SS bit mode supports SONET (00) or SDH (10) values and defines the value of the SS bits for unequipped signal insertion. In normal mode, SS bits can be passed through or overwritten with a provisioned value. All SS bit provisioning is done at a STM-16 level affecting all AU-3s. The B1 error mask can be extracted serially on the ROHDAT interface, and the B2 error mask can be extracted serially on the local orderwire, express orderwire, and orderwire clock pins.
Section overhead (RSOH) and line overhead (MSOH) termination, and path overhead monitoring for one SONET STS-192 (SDH STM-64) or four STS-48 (STM-16) signals. Supports any valid combination of STS-1 and concatenated payloads from STS-3c to STS-192c. Microprocessor interface configurable to operate with most commercial microprocessors. IEEE (R) 1149.1 port with memory built-in self-test (BIST), scan, and boundary scan (JTAG). Low-power 2.5 V operation with 3.3 V (5 V tolerant) inputs and outputs. EIA (R)-644, IEEE 1596.3 compliant LVDS buffers*. 600-pin LBGA package. -40 C to +85 C temperature range.
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STS-192/STM-64 (Line Interface)
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Provides a 16-bit (or 4 x 4-bit) wide, 622 MHz differential line interface. Synchronizes to the receive data frames and detects severely errored framing (SEF) and loss of frame (LOF). Also inserts the framing bytes (A1 and A2) in the transmit data. Supports enhanced framing (A1, A1, A2, A2). Performs frame-synchronous scrambling and descrambling of the STS-192/STS-48 data, and loss of signal (LOS) is detected. Extracts the 64-byte or 16-byte section trace message (J0) from the receive data and optionally stores it in, or compares it to, an internal register bank. Unstable or mismatched messages are detected, and path alarm indication signal (AIS) may be optionally inserted in the drop data. Optionally inserts a 64-byte or 16-byte section trace message or a fixed pattern in the J0 byte of the transmit data.
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* Refer to LVDS Receiver Buffer Capabilities section on page 169 for additional details.
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Table of Contents
Contents Page
Features ................................................................................................................................................................... 1 General .................................................................................................................................................................. 1 STS-192/STM-64 (Line Interface).......................................................................................................................... 1 Add/Drop (Equipment Interface) .......................................................................................................................... 12 Applications ............................................................................................................................................................ 12 Description.............................................................................................................................................................. 13 Block Diagrams.................................................................................................................................................... 13 Glossary............................................................................................................................................................... 14 Receive Direction Overview................................................................................................................................. 15 Transmit Direction Overview................................................................................................................................ 15 STS-192 Mode Options ....................................................................................................................................... 16 TOH Transparency............................................................................................................................................ 16 Regenerator Loopback...................................................................................................................................... 16 Device Mode Setup.............................................................................................................................................. 16 Pin Information ....................................................................................................................................................... 17 Functional Description ............................................................................................................................................ 47 Receive STS-192 Line Interface .......................................................................................................................... 47 Loss-of-Signal (LOS) Detector .......................................................................................................................... 47 Framer (A1 and A2)........................................................................................................................................... 48 Descrambler ...................................................................................................................................................... 50 Time-Slot Interchanger (TSI)............................................................................................................................. 50 Receive Transport Overhead (TOH) Processor................................................................................................... 52 Receive Overhead Serial Links ......................................................................................................................... 52 Section Trace (J0) ............................................................................................................................................. 53 Section Growth (Z0) .......................................................................................................................................... 54 Section BIP-8 (B1)............................................................................................................................................. 54 Section BIP-8 (B1) Errors Serial Access ........................................................................................................... 54 Local Orderwire (E1) ......................................................................................................................................... 55 Section User Channel (F1)................................................................................................................................ 55 Section Data Communications Channel (D1, D2, and D3) ............................................................................... 55 Line BIP-8 (B2).................................................................................................................................................. 56 Line BIP-8 (B2) Errors Serial Access ................................................................................................................ 58 APS Channel (K1 and K2)................................................................................................................................. 58 Line Data Communication Channel (D4--D12) ................................................................................................ 60 Synchronization Status (S1).............................................................................................................................. 60 STS-192 Line Remote Error Indication (M1) ..................................................................................................... 61 Express Orderwire (E2)..................................................................................................................................... 61 Receive STS Path Processor .............................................................................................................................. 61 1:4 Demultiplex TSI ........................................................................................................................................... 62 Receive Pointer Processor................................................................................................................................ 62 Receive Path Overhead (POH) Processor........................................................................................................ 69 Receive Payload Drop Interface .......................................................................................................................... 76 STS-12 Overhead Insertion and Scrambling..................................................................................................... 77 Drop Interface Output Format ........................................................................................................................... 78 Data Path Parity ................................................................................................................................................ 79 Regenerator Loopback (STS-192 Mode Only) .................................................................................................... 80 Transmit Payload Add Interface........................................................................................................................... 80 STS-12 Framing, Descrambling, and TOH Processing..................................................................................... 81 Transmit Synchronization Buffer ....................................................................................................................... 82 Add Interface Framing (A1 and A2)................................................................................................................... 82 4:1 Time-Slot Multiplex (TSM)........................................................................................................................... 84 2 Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Table of Contents (continued)
Contents Page
Transmit Transport Overhead (TOH) Processor.................................................................................................. 84 TOH Transparency............................................................................................................................................ 85 Transmit Overhead Serial Links ........................................................................................................................ 86 Section Trace/Section Growth (J0/Z0) .............................................................................................................. 86 Section BIP-8 (B1)............................................................................................................................................. 87 Local Orderwire (E1) ......................................................................................................................................... 87 Section User Channel (F1)................................................................................................................................ 87 Section Data Communications Channel (D1, D2, and D3) ............................................................................... 88 STS Payload Pointer (H1 and H2) .................................................................................................................... 88 Line BIP-8 (B2).................................................................................................................................................. 89 APS Channel (K1 and K2)................................................................................................................................. 90 Line Data Communication Channel (D4--D12) ................................................................................................ 90 Synchronization Status (S1).............................................................................................................................. 91 STS-192 Line Remote Error Indication (M1) ..................................................................................................... 91 Express Orderwire (E2)..................................................................................................................................... 92 Transmit STS-192 Line Interface ......................................................................................................................... 92 Time-Slot Multiplexer (TSM).............................................................................................................................. 92 Scrambler .......................................................................................................................................................... 92 Data Path Parity ................................................................................................................................................ 92 Microprocessor Interface ........................................................................................................................................ 93 Architecture.......................................................................................................................................................... 93 Transfer Error Acknowledge (TEA_N)............................................................................................................... 93 Interrupt Structure ............................................................................................................................................. 93 Parity Bits .......................................................................................................................................................... 94 Clock Domains .................................................................................................................................................. 94 Persistency Registers .......................................................................................................................................... 96 Register Description............................................................................................................................................. 96 Software Reset .................................................................................................................................................... 96 Device-Level Registers ...................................................................................................................................... 110 Line Terminating Equipment (LTE) Registers.................................................................................................... 115 LTE Common Registers .................................................................................................................................. 115 LTE J0 Access Registers ................................................................................................................................ 117 Signal Degrade/Signal Fail Registers.............................................................................................................. 119 LTE Receive Channel 1, 2, 3, and 4 Registers ............................................................................................... 122 LTE Transmit Common Registers...................................................................................................................... 128 LTE Transmit Channel Registers .................................................................................................................... 130 Equipment (EQPT) Registers ............................................................................................................................ 134 EQPT Common Registers............................................................................................................................... 134 EQPT Receive Drop STS-48 Channel Registers 1--4 ................................................................................... 137 EQPT Transmit Add STS-48 Channel Registers 1--4.................................................................................... 139 Path Overhead (POH) Registers ....................................................................................................................... 144 STS-12, STS-1 Level POH Registers ............................................................................................................. 145 STS-192 Level POH Registers........................................................................................................................ 149 STS-192 Level Path Trace Registers.............................................................................................................. 154 STS-48 Level POH Registers.......................................................................................................................... 155 Absolute Maximum Ratings.................................................................................................................................. 166 Handling Precautions ........................................................................................................................................... 166 Recommended Operating Conditions .................................................................................................................. 166 Electrical Characteristics ...................................................................................................................................... 167 Power Sequencing............................................................................................................................................. 167 Low-Voltage Differential Signal (LVDS) Buffers................................................................................................. 167 Agere Systems Inc. 3
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Table of Contents (continued)
Contents Page
LVDS Receiver Buffer Capabilities.................................................................................................................. 169 Timing Characteristics .......................................................................................................................................... 172 Receive Data Interface ...................................................................................................................................... 172 Receive STS-48/STS-192 Data ...................................................................................................................... 172 Receive Transport Overhead Interface.............................................................................................................. 173 Receive Local Orderwire ................................................................................................................................. 173 Receive Section User...................................................................................................................................... 173 Receive Express Orderwire............................................................................................................................. 174 Receive Section Data Com ............................................................................................................................. 174 Receive Line Data Com .................................................................................................................................. 174 Receive Overhead Serial Link......................................................................................................................... 175 Transmit Data Interface ..................................................................................................................................... 176 Transmit STS-48/STS-192 Data ..................................................................................................................... 176 Transmit Frame ............................................................................................................................................... 177 Transmit Transport Overhead Interface............................................................................................................. 178 Transmit Local Orderwire ................................................................................................................................ 178 Transmit Section User..................................................................................................................................... 178 Transmit Express Orderwire............................................................................................................................ 178 Transmit Section Data Com ............................................................................................................................ 179 Transmit Line Data Com ................................................................................................................................. 179 Transmit Overhead Serial Link........................................................................................................................ 180 Receive Drop Interface ...................................................................................................................................... 181 Drop Clock, Drop Frame, and Drop Data ........................................................................................................ 181 Receive Drop Section Data Com .................................................................................................................... 182 Transmit Add Interface....................................................................................................................................... 183 Transmit Add Data .......................................................................................................................................... 183 Transmit Add Section Data Com..................................................................................................................... 183 Microprocessor Interface Timing........................................................................................................................ 183 Synchronous Mode ......................................................................................................................................... 183 Asynchronous Mode........................................................................................................................................ 186 Use of a Synchronous Microprocessor with the TSOT0410G4 in Asynchronous Mode ................................. 188 Outline Diagram.................................................................................................................................................... 189 600-Pin LBGA .................................................................................................................................................... 189 Ordering Information............................................................................................................................................. 190
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
List of Figures
Contents Page
Figure 1. TSOT0410G4 Block Diagram, STS-192 Mode ...................................................................................... 13 Figure 2. TSOT0410G4 Block Diagram, STS-48 Mode ........................................................................................ 14 Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages ............................................................. 35 Figure 4. Framer FSM ........................................................................................................................................... 49 Figure 5. Example of STS-192 SD Detection (10-5 BER) and Clearing (10-6 BER) ............................................. 57 Figure 6. Timing Diagram for RFRM ..................................................................................................................... 60 Figure 7. Pointer Interpreter State Machine .......................................................................................................... 63 Figure 8. STS-12 Data Outputs and Timing .......................................................................................................... 79 Figure 9. TSOT0410G4 Timing Domains .............................................................................................................. 95 Figure 10. Persistency Register Operation ............................................................................................................ 96 Figure 11. Path Register Structure ...................................................................................................................... 144 Figure 12. LVDS Driver and Receiver and Associated Internal Components ..................................................... 168 Figure 13. LVDS Driver and Receiver ................................................................................................................. 168 Figure 14. LVDS Driver ....................................................................................................................................... 168 Figure 15. Receive Data Timing .......................................................................................................................... 172 Figure 16. Receive Data Communication Channels Timing ................................................................................ 173 Figure 17. Receive Overhead Serial Timing ........................................................................................................ 175 Figure 18. Transmit Data Timing ......................................................................................................................... 176 Figure 19. Transmit Frame Timing ...................................................................................................................... 177 Figure 20. Transmit Data Communication Channels Timing ............................................................................... 178 Figure 21. Transmit Overhead Serial Timing ....................................................................................................... 180 Figure 22. Receive Frame Timing (Pointer Processor Bypassed) ...................................................................... 181 Figure 23. Receive Frame Timing (Pointer Processor Active) ............................................................................ 182 Figure 24. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1) ................................................. 184 Figure 25. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) ................................................. 185 Figure 26. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0) ............................................... 186 Figure 27. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0) ............................................... 187
Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
List of Tables
Contents Page
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order....................................................................... 17 Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order ..................................................................... 22 Table 3. Pin Descriptions--System Control ........................................................................................................... 26 Table 4. Pin Descriptions--Receive Line Interface ................................................................................................ 27 Table 5. Pin Descriptions--Transmit Line Interface ............................................................................................... 28 Table 6. Pin Descriptions--LVDS Reference, Line Interface ................................................................................. 30 Table 7. Pin Descriptions--Receive Drop Equipment Interface ............................................................................. 31 Table 8. Pin Descriptions--Transmit Add Equipment Interface ............................................................................. 33 Table 9. Pin Descriptions--LVDS Reference, Equipment Interface....................................................................... 35 Table 10. Pin Descriptions--Transport Overhead Interface................................................................................... 36 Table 11. Pin Descriptions--Microprocessor Interface .......................................................................................... 42 Table 12. Pin Descriptions--JTAG Interface.......................................................................................................... 43 Table 13. Pin Descriptions--PLL References ........................................................................................................ 44 Table 14. Pin Descriptions--Power and Ground.................................................................................................... 44 Table 15. Pin Summary .......................................................................................................................................... 46 Table 16. LOS Detector Register Summary ........................................................................................................... 48 Table 17. Framer Register Summary ..................................................................................................................... 50 Table 18. Descrambler Register Summary ............................................................................................................ 50 Table 19. STS-192 Byte Ordering .......................................................................................................................... 51 Table 20. STS-48 Byte Ordering ............................................................................................................................ 51 Table 21. Receive Overhead Serial Links Register Summary ............................................................................... 52 Table 22. J0 Register Summary ............................................................................................................................. 54 Table 23. B1 Register Summary ............................................................................................................................ 55 Table 24. BER Threshold Time and Error Limits for Line SD and SF Detection .................................................... 56 Table 25. B2 Register Summary ............................................................................................................................ 58 Table 26. APS Channel (K1 and K2) Register Summary ....................................................................................... 59 Table 27. Synchronization Status (S1) Register Summary .................................................................................... 61 Table 28. Line REI (M1) Register Summary........................................................................................................... 61 Table 29. STS-12 Byte Ordering ............................................................................................................................ 62 Table 30. Pointer Interpreter Register Summary.................................................................................................... 64 Table 31. Elastic Store Register Summary............................................................................................................. 65 Table 32. Pointer Generator Bypass Register Summary ....................................................................................... 65 Table 33. AIS-P Insertion Conditions ..................................................................................................................... 66 Table 34. Path AIS Insertion Register Summary.................................................................................................... 67 Table 35. Concatenation Register Summary.......................................................................................................... 68 Table 36. Pointer Justification Binning Register Summary..................................................................................... 68 Table 37. J1 Register Summary ............................................................................................................................. 70 Table 38. BER Threshold Time Window and Error Limits for Path SF Detection................................................... 71 Table 39. Time Window Sizes for Path SF Detection............................................................................................. 71 Table 40. B3 Register Summary ............................................................................................................................ 72 Table 41. STS Path Signal Label Assignments...................................................................................................... 73 Table 42. Path Signal Label (C2) Alarm Scenarios ................................................................................................ 74 Table 43. C2 Register Summary ............................................................................................................................ 75 Table 44. RDI-P Codes and Interpretation ............................................................................................................. 76 Table 45. G1 Register Summary ............................................................................................................................ 76 Table 46. Path Alarm Information Encoding........................................................................................................... 77 Table 47. Line Alarm Information Encoding ........................................................................................................... 78 Table 48. Drop Interface Overhead and Scrambling Register Summary ............................................................... 78 Table 49. Timing Enable Bit Definitions.................................................................................................................. 79 Table 50. Receive Data Path Parity Register Summary......................................................................................... 79 Table 51. LTE Transmit Channel Registers--Regenerator Loopback Summary................................................... 80 6 Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
List of Tables (continued)
Contents Page
Table 52. Regenerator Loopback Bit Definitions .................................................................................................... 80 Table 53. Path AIS Insertion Encoding................................................................................................................... 81 Table 54. Add Interface Overhead and Scrambling Register Summary................................................................. 82 Table 55. Transmit Synchronization Buffer Register Summary.............................................................................. 82 Table 56. Frame Pulse Provisioning Bit Definitions................................................................................................ 84 Table 57. Transmit Framing Register Summary..................................................................................................... 84 Table 58. LTE Transmit Channel Registers--TOH Transparency Summary ......................................................... 85 Table 59. TOH Transparency Bit Definitions .......................................................................................................... 85 Table 60. Transmit Overhead Serial Links Register Summary .............................................................................. 86 Table 61. Transmit Section Trace (J0) Register Summary .................................................................................... 87 Table 62. Transmit B1 Register Summary ............................................................................................................. 87 Table 63. Transmit STS Payload Pointer Register Summary ................................................................................ 89 Table 64. Transmit B2 Register Summary ............................................................................................................. 89 Table 65. K Byte Select Control Bits ...................................................................................................................... 90 Table 66. Transmit APS Channel (K1K2) Register Summary ................................................................................ 90 Table 67. Transmit Synchronization Status (S1) Register Summary ..................................................................... 91 Table 68. Transmit M1 Register Summary............................................................................................................. 91 Table 69. Transmit Line Scrambler Register Summary.......................................................................................... 92 Table 70. Transmit Data Path Parity Register Summary........................................................................................ 92 Table 71. Register Summary.................................................................................................................................. 97 Table 72. Interrupt Status (RO) ............................................................................................................................ 110 Table 73. Interrupt Status Mask (R/W) ................................................................................................................. 111 Table 74. Chip ID (RO)......................................................................................................................................... 111 Table 75. Chip Vintage (RO) ................................................................................................................................ 111 Table 76. Scratch Pad, Clock Loss Alarm (R/W).................................................................................................. 112 Table 77. Chip-Level Maintenance (R/W) ............................................................................................................ 112 Table 78. Chip Status (RO) .................................................................................................................................. 112 Table 79. Clock Loss Alarm/PM Clock Detection (W1C)...................................................................................... 113 Table 80. Clock Loss Alarm/PM Clock Detection Mask (R/W) ............................................................................. 114 Table 81. Software Chip Reset (WO) ................................................................................................................... 114 Table 82. LTE Interrupt Status (RO)..................................................................................................................... 115 Table 83. LTE Interrupt Status Mask (R/W) ......................................................................................................... 116 Table 84. Section Trace (J0) Access Maintenance (R/W).................................................................................... 117 Table 85. J0 Access Done (W1C) ........................................................................................................................ 118 Table 86. J0 Access Message Start (WO) ........................................................................................................... 118 Table 87. J0 Access Message Buffers 1--32 (R/W) ............................................................................................ 118 Table 88. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-3) (R/W) ................................ 119 Table 89. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-4) (R/W) ................................ 119 Table 90. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-5) (R/W) ................................ 119 Table 91. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-6) (R/W) ................................ 119 Table 92. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-7) (R/W) ................................ 119 Table 93. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-8) (R/W) ................................ 120 Table 94. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-9) (R/W) ................................ 120 Table 95. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-10) (R/W) ............................... 120 Table 96. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-3) (R/W) ................................................... 120 Table 97. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-4) (R/W) ................................................... 120 Table 98. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-5) (R/W) ................................................... 120 Table 99. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-6) (R/W) ................................................... 121 Table 100. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-7) (R/W) ................................................. 121 Table 101. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-8) (R/W) ................................................. 121 Table 102. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-9) (R/W) ................................................. 121 Agere Systems Inc. 7
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
List of Tables (continued)
Contents Page
Table 103. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-4) (R/W) ................................................... 121 Table 104. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-5) (R/W) ................................................... 121 Table 105. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-6) (R/W) ................................................... 121 Table 106. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-7) (R/W) ................................................... 122 Table 107. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-8) (R/W) ................................................... 122 Table 108. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-9) (R/W) ................................................... 122 Table 109. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-10) (R/W).................................................. 122 Table 110. LTE Receive Channel 1 Provisioning (R/W)....................................................................................... 122 Table 111. LTE Receive Channel 1 Maintenance (R/W)...................................................................................... 123 Table 112. LTE Receive Channel 1 Loss-of-Signal (LOS) Threshold (R/W)........................................................ 123 Table 113. LTE Receive Channel 1 K Byte Status (RO) ...................................................................................... 123 Table 114. LTE Receive Channel 1 S1 Byte Status (RO) .................................................................................... 123 Table 115. LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) ..................................................... 124 Table 116. LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask (R/W)............................................. 124 Table 117. LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO)................................................... 124 Table 118. LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) ............................................... 125 Table 119. LTE Receive Channel 1 Nonservice-Affecting Interrupt Mask (R/W) ................................................. 126 Table 120. LTE Receive Channel 1 Nonservice-Affecting Persistency Alarm (RO)............................................. 127 Table 121. LTE Receive Channel 1 Performance Monitoring (RO) ..................................................................... 127 Table 122. LTE Receive Channel 1 REI-L Performance Monitoring (L) (RO)...................................................... 127 Table 123. LTE Receive Channel 1 REI-L Performance Monitoring (U) (RO) ..................................................... 127 Table 124. LTE Receive Channel 1 CV-L Performance Monitoring (L) (RO)....................................................... 127 Table 125. LTE Receive Channel 1 CV-L Performance Monitoring (U) (RO) ...................................................... 127 Table 126. LTE Receive Channel 1 CV-S Performance Monitoring (RO)............................................................ 128 Table 127. LTE Transmit--Frame Pulse Offset Count (R/W) .............................................................................. 128 Table 128. LTE Transmit--Add Interface Self-Sync Option (R/W)....................................................................... 128 Table 129. LTE Transmit--B1 Corrupt Frame Count (R/W)................................................................................. 128 Table 130. LTE Transmit--B2 Corrupt Frame Count (R/W)................................................................................. 128 Table 131. LTE Transmit--M1 Corrupt Frame Count (R/W) ................................................................................ 129 Table 132. LTE Transmit--TFRM S1 Byte (RO) .................................................................................................. 129 Table 133. LTE Transmit--Interrupt Alarm Register (W1C)................................................................................. 129 Table 134. LTE Transmit--Interrupt Mask Register (R/W)................................................................................... 130 Table 135. LTE Transmit Channel 1 Provisioning (R/W)...................................................................................... 130 Table 136. LTE Transmit Bit Assignment ............................................................................................................. 131 Table 137. LTE Transmit Channel 1 Maintenance (R/W)..................................................................................... 131 Table 138. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 (R/W)................................. 131 Table 139. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2 (R/W)................................. 131 Table 140. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3 (R/W)................................. 131 Table 141. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4 (R/W)................................. 132 Table 142. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 (R/W) ................................................... 132 Table 143. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2 (R/W) ................................................... 132 Table 144. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3 (R/W) ................................................... 132 Table 145. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4 (R/W) ................................................... 132 Table 146. LTE Transmit Channel 1 K1K2 Byte Insert Values (R/W) .................................................................. 132 Table 147. LTE Transmit Channel 1 S1 Byte Insert Value (R/W) ........................................................................ 132 Table 148. LTE Transmit Channel 1 Interrupt Alarm (W1C) ................................................................................ 133 Table 149. LTE Transmit Channel 1 Interrupt Alarm Mask (R/W)........................................................................ 133 Table 150. EQPT Interrupt Status (RO) ............................................................................................................... 134 Table 151. EQPT Interrupt Mask (R/W) ............................................................................................................... 135 Table 152. Receive Drop Common Service-Affecting Alarm (W1C) .................................................................... 136 Table 153. Receive Drop Common Service-Affecting Alarm Mask (R/W)............................................................ 136 8 Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
List of Tables (continued)
Contents Page
Table 154. Receive Drop STS-48 Channel Provisioning Register 1 (R/W).......................................................... 137 Table 155. J0 Trace--STS-12 Channel 1 (R/W) .................................................................................................. 137 Table 156. J0 Trace--STS-12 Channel 2 (R/W) .................................................................................................. 137 Table 157. J0 Trace--STS-12 Channel 3 (R/W) .................................................................................................. 137 Table 158. J0 Trace--STS-12 Channel 4 (R/W) .................................................................................................. 137 Table 159. Receive Drop STS-48 Channel Nonservice-Affecting Alarm (W1C) .................................................. 138 Table 160. Receive Drop STS-48 Channel Nonservice Affecting Alarm Mask (R/W).......................................... 138 Table 161. Transmit Add STS-48 Channel Provisioning (R/W)............................................................................ 139 Table 162. J0 Status Register--1 (RO)................................................................................................................ 139 Table 163. J0 Status Register--2 (RO)................................................................................................................ 139 Table 164. J0 Status Register--3 (RO)................................................................................................................ 139 Table 165. J0 Status Register--4 (RO)................................................................................................................ 139 Table 166. AIS Insert Status Register, STS-12 Channel #1 (RO)........................................................................ 140 Table 167. AIS Insert Status Register, STS-12 Channel #2 (RO)........................................................................ 140 Table 168. AIS Insert Status Register, STS-12 Channel #3 (RO)........................................................................ 141 Table 169. AIS Insert Status Register, STS-12 Channel #4 (RO)........................................................................ 141 Table 170. Transmit Add STS-48 Channel Alarm (W1C)..................................................................................... 142 Table 171. Transmit Add STS-48 Channel Alarm Mask (R/W) ............................................................................ 143 Table 172. STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 (R/W) ........................................... 145 Table 173. STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 (R/W) .......................................... 145 Table 174. STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) .................. 145 Table 175. STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) ................ 146 Table 176. STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) .................. 146 Table 177. STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO)................. 146 Table 178. STS-1 #1 Path Overhead Provisioning (R/W) .................................................................................... 146 Table 179. STS-1 #1 Path Overhead Maintenance (R/W) ................................................................................... 146 Table 180. STS-1 #1 Path Overhead Status (RO) ............................................................................................... 147 Table 181. STS-1 #1 Alarm Interrupt Status (W1C) ............................................................................................. 147 Table 182. STS-1 #1 Alarm Interrupt Status Mask (R/W) .................................................................................... 147 Table 183. STS-1 #1 Alarm Persistency (RO)...................................................................................................... 148 Table 184. STS-1 #1 PM Last Second Indicators (RO)........................................................................................ 148 Table 185. STS-1 #1 Last Second CV-P Count (RO) .......................................................................................... 148 Table 186. STS-1 #1 Last Second REI-P Count (RO) ......................................................................................... 148 Table 187. Path Overhead (POH) Interrupt Status (RO)...................................................................................... 149 Table 188. Path Overhead (POH) Interrupt Status Mask (R/W)........................................................................... 149 Table 189. STS-1 Signal Fail Detect Threshold, Window Size Select 0 (R/W) .................................................... 150 Table 190. STS-1 Signal Fail Clear Threshold, Window Size Select 0 (R/W)...................................................... 150 Table 191. STS-1 Signal Fail Detect Threshold, Window Size Select 1 (R/W) .................................................... 150 Table 192. STS-1 Signal Fail Clear Threshold, Window Size Select 1 (R/W)...................................................... 150 Table 193. STS-Nc Signal Fail Detect Threshold, Window Size Select 2 (R/W).................................................. 151 Table 194. STS-Nc Signal Fail Clear Threshold, Window Size Select 2 (R/W) ................................................... 151 Table 195. STS-Nc Signal Fail Detect Threshold, Window Size Select 3 (R/W).................................................. 151 Table 196. STS-Nc Signal Fail Clear Threshold, Window Size Select 3 (R/W) ................................................... 151 Table 197. STS-Nc Signal Fail Detect Threshold, Window Size Select 4 (R/W).................................................. 152 Table 198. STS-Nc Signal Fail Clear Threshold, Window Size Select 4 (R/W) ................................................... 152 Table 199. STS-Nc Signal Fail Detect Threshold, Window Size Select 5 (R/W).................................................. 152 Table 200. STS-Nc Signal Fail Clear Threshold, Window Size Select 5 (R/W) ................................................... 152 Table 201. STS-Nc Signal Fail Detect Threshold, Window Size Select 6 (R/W).................................................. 152 Table 202. STS-Nc Signal Fail Clear Threshold, Window Size Select 6 (R/W) ................................................... 152 Table 203. STS-Nc Signal Fail Detect Threshold, Window Size Select 7 (R/W).................................................. 153 Table 204. STS-Nc Signal Fail Clear Threshold, Window Size Select 7 (R/W) ................................................... 153 Agere Systems Inc. 9
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
List of Tables (continued)
Contents Page
Table 205. Signal Fail Window Size 0 (R/W)........................................................................................................ 153 Table 206. Signal Fail Window Size 1 (R/W)........................................................................................................ 153 Table 207. Signal Fail Window Size 2 (R/W)........................................................................................................ 153 Table 208. Signal Fail Window Size 3 (R/W)........................................................................................................ 153 Table 209. Path Trace Access Control (R/W) ...................................................................................................... 154 Table 210. Path Trace Access Complete Status (W1C) ...................................................................................... 154 Table 211. Path Trace Access Start..................................................................................................................... 154 Table 212. Path Trace Buffer Word #1--Word #32.............................................................................................. 154 Table 213. STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (RO) ......................................................... 155 Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) .............................................. 155 Table 215. STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (RO) ....................................................... 157 Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) ............................................ 158 Table 217. STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (RO) ....................................................... 159 Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) ............................................ 160 Table 219. STS-48 Channel Path Trace Control (R/W) ....................................................................................... 161 Table 220. S/W Concatenation Map STS-1 #1 to STS-1 #12 (R/W).................................................................... 161 Table 221. S/W Concatenation Map STS-1 #13 to STS-1 #24 (R/W).................................................................. 161 Table 222. S/W Concatenation Map STS-1 #25 to STS-1 #36 (R/W).................................................................. 162 Table 223. S/W Concatenation Map STS-1 #37 to STS-1 #48 (R/W).................................................................. 162 Table 224. S/W Concatenation Mask STS-1 #1 to STS-1 #12 (R/W) .................................................................. 162 Table 225. S/W Concatenation Mask STS-1 #13 to STS-1 #24 (R/W) ................................................................ 162 Table 226. S/W Concatenation Mask STS-1 #25 to STS-1 #36 (R/W) ................................................................ 162 Table 227. S/W Concatenation Mask STS-1 #37 to STS-1 #48 (R/W) ................................................................ 163 Table 228. Received Concatenation Map STS-1 #1 to STS-1 #12 (RO) ............................................................. 163 Table 229. Received Concatenation Map STS-1 #13 to STS-1 #24 (RO) ........................................................... 163 Table 230. Received Concatenation Map STS-1 #25 to STS-1 #36 (RO) ........................................................... 163 Table 231. Received Concatenation Map STS-1 #37 to STS-1 #48 (RO) ........................................................... 163 Table 232. STS-48 Channel Path Alarms 1 (W1C) .............................................................................................. 164 Table 233. STS-48 Channel Path Alarms 1 Mask (W1C) .................................................................................... 165 Table 234. Absolute Maximum Ratings................................................................................................................ 166 Table 235. Recommended Operating Conditions ................................................................................................ 166 Table 236. Thermal Resistance--Junction to Ambient ........................................................................................ 167 Table 237. LVDS Driver dc Data .......................................................................................................................... 169 Table 238. LVDS Driver ac Data .......................................................................................................................... 169 Table 239. LVDS Driver Reference Data ............................................................................................................. 170 Table 240. LVDS Receiver Data .......................................................................................................................... 170 Table 241. Receive Payload Add Interface .......................................................................................................... 170 Table 242. Receive Payload Drop Interface......................................................................................................... 171 Table 243. LVTTL 3.3 V Logic Interface Characteristics ...................................................................................... 171 Table 244. Receive Data Timing .......................................................................................................................... 172 Table 245. RLCLOW/RSUSER/REXPOW Timing ............................................................................................... 174 Table 246. RSDCC Timing ................................................................................................................................... 174 Table 247. RLDCC Timing ................................................................................................................................... 174 Table 248. Receive Overhead Serial Timing........................................................................................................ 175 Table 249. Transmit Data Timing ......................................................................................................................... 176 Table 250. Transmit Frame Timing ...................................................................................................................... 177 Table 251. TLCLOW/TSUSER/TEXPOW Timing................................................................................................. 178 Table 252. TSDCC Timing ................................................................................................................................... 179 Table 253. TLDCC Timing.................................................................................................................................... 179 Table 254. Transmit Overhead Serial Timing....................................................................................................... 181 Table 255. Drop Frame Timing (Pointer Processor Bypassed)............................................................................ 181 10 Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
List of Tables (continued)
Contents Page
Table 256. Drop Frame Timing (Pointer Processor Active).................................................................................. 182 Table 257. RDDCC Timing................................................................................................................................... 182 Table 258. TADCC Timing ................................................................................................................................... 183 Table 259. TA_N/TEA_N Cycle Termination for Synchronous Write Cycle ......................................................... 184 Table 260. Microprocessor Interface Synchronous Write Cycle Specifications ................................................... 184 Table 261. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle ......................................................... 185 Table 262. Microprocessor Interface Synchronous Read Cycle Specifications ................................................... 185 Table 263. Microprocessor Interface Asynchronous Write Cycle Specifications.................................................. 186 Table 264. TA_N/TEA_N Cycle Termination for Asynchronous Write Cycle ....................................................... 187 Table 265. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle ....................................................... 187 Table 266. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................. 187
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Outputs path alarm information for each receive STS in the overhead bytes of the drop data (E1/F1). Optional TOH transparency capability on the line interface to/from the TOH on the equipment interface. Either full TOH transparency, or just line overhead (MSOH) transparency with section overhead (RSOH) insertion/extraction, may be selected. In the receive direction, the section overhead will be used for path alarm information if section overhead transparency is not selected. The pointer processor will be automatically bypassed if any of these options are selected. Optional loopback of the receive data and overhead towards the transmit line interface in STS-192 mode. The transmit clock is replaced by the receive clock at the 622 MHz level external to the chip, with the add interface buffers used to align the data between the receive and transmit clock domains. The TFRM signal is replaced by receive frame timing to transfer from the receive to the transmit clock domains. Active per-STS-48 transmit line AIS insert controls during receive LOS, receive LOF, or R_CLK failure while in regenerator loopback mode. The add interface self-sync provides the option to use frame timing being recovered from one of the add pseudo-STS-12 links as the transmit frame sync instead of TFRM. The resynchronizing is inhibited if the selected add pseudo-STS-12 link is out of frame (OOF).
Features (continued)
Add/Drop (Equipment Interface)
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Provides sixteen 1-bit serial 622 MHz (STS-12 rate) differential data links at the add and drop interfaces. Path overhead and SPE timing indication is provided by the drop interface. Clock recovery and data skew compensation are provided at the add interface. Transmit frame alignment synchronization may be controlled via an input (TFRM), or may optionally derived from any one of sixteen add inputs. Interprets the pointer bytes (H1, H2) for each receive STS and detects loss of pointer (LOP) and path AIS. Generates new pointer bytes in each drop STS to adapt the receive data to the drop frequency and phase. Pointer generation can be bypassed for synchronous applications. Optionally inserts path AIS in all drop STS pointer bytes during LOS, LOF, SEF, or line AIS (MS-AIS) defects. Optionally inserts path AIS in each drop STS due to LOP or path AIS defects in the corresponding receive STS, or under software control. Inserts pointer bytes in the transmit data based on values received in the transport overhead bytes of the add data. Optionally inserts path AIS in each transmit STS under control by software, or through bits in the transport overhead of the add data. Extracts the 64-byte or 16-byte path trace message (J1) from up to four selectable receive STS channels (one per STS-48), and stores it in an internal register bank. Optionally compares the message to an expected message stored in the internal register bank and detects an unstable or mismatched message. Calculates, detects, and accumulates path BIP-8 errors (B3) for each receive STS (provisionable based on bit or block errors). Provides signal fail detection with provisionable BER. Extracts and counts path REI for each receive STS (G1). Detects path unequipped, payload label mismatch (PLM), and optionally, payload defect indication (PDI) in the C2 byte of each receive STS. Optionally inserts unequipped signal in each transmit STS under software control. Detects 1-bit and enhanced path RDI (3-bit) in each receive STS (G1).
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Applications
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SONET/SDH add/drop multiplex equipment. SONET/SDH terminal equipment. SONET/SDH digital cross connect equipment. SONET/SDH regenerator equipment. SONET/SDH test equipment. ATM or packet over SONET/SDH equipment.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Description
The TSOT0410G4 is used to terminate the transport overhead in a single SONET STS-192 (SDH STM-64) signal or four SONET STS-48 (SDH STM-16) signals. It monitors the STS path pointers and overhead in the receive data and provides timing signals for payload mapping devices on the equipment side. The TSOT0410G4 can be provisioned to support any mix of STS-1 (AU-3) or STS-Nc (AU-4-Xc) payloads from a single STS-192c (AU-4-64c) channel to 192 STS-1 (AU-3) channels. Block diagrams are shown in Figure 1 and Figure 2. The TSOT0410G4 is a 2.5 V, 0.25 m high-density device which is packaged in a 600-pin laminate ball grid array (LBGA). The I/O circuitry uses a 3.3 V, 0.25 m technology (5 V tolerant) for LVTTL, and LVDS for high-speed signals. The microprocessor interface allows an external processor to access the TSOT0410G4 for configuration and maintenance. The microprocessor interface is designed to support various 16-bit microprocessors with minimal glue logic. The TSOT0410G4 includes an IEEE 1149.1 compliant JTAG port to support boundary scan and memory BIST testing of the device.
Block Diagrams
Figure 1, below, is a block diagram of the TSOT0410G4 when operating in STS-192 mode (pin AM17, STS_MODE = 0). Figure 2 on page 14 is a block diagram of the TSOT0410G4 when operating in quad STS-48 mode (pin AM17, STS_MODE = 1). For convenience, two symbol sets are provided for the transmit and receive line interface pins, based on the mode of the device. Both sets of symbols are included in the pin tables.
TLDCC_[1--4] TOHDAT_[1--4]_[1:0] TOH_CLK_[1--4] TOW_CLK_[1--4] TSD_CLK_[1--4] TLD_CLK_[1--4]
ADDRESS_[15:0]
TLCLOW_[1--4] TEXPOW_[1--4]
TSUSER_[1--4] TSDCC_[1--4]
TOHEN_[1--4] TOHFP_[1--4]
PARITY_[1:0]
DATA_[15:0]
RW_N
CS_N
DS_N
TS_N
TFRM T_CLK X4 TRANSMIT STS-48 TRANSMIT STS-192 TRANSPORT OVERHEAD LINE PROCESSOR INTERFACE X4 STS_MODE = 0 R_CLK_1 SECTION TRACE BUFFER X4 RECEIVE STS-48 RECEIVE STS-192 TRANSPORT OVERHEAD LINE PROCESSOR INTERFACE RECEIVE PATH OVERHEAD PROCESSOR RECEIVE DROP ALIGNER X4 PATH TRACE BUFFER STS PATH PROCESSING BLOCK X4 RECEIVE PAYLOAD DROP INTERFACE DFRM D_CLK DDATA_[16:1] DCTL_[1--4] RDDCC_[16:1] RDDCK_[1--4] JTAG INTERFACE MICROPROCESSOR INTERFACE RST_N TD[15:0] X4 TRANSMIT PAYLOAD ADD INTERFACE HIZ_N TADCC_[16:1] TADCK ADATA_[16:1]
T_CLKO_1
RD[15:0]
RFRM[1--4]
RECEIVE POINTER PROCESSOR R_CLKO_1
DRPBYP
TMS
TCK
REXPOW_[1--4]
RSDCC_[1--4]
ROHDAT_[1--4]_[1:0]
RSUSER_[1--4]
RLCLOW_[1--4]
RLDCC_[1--4]
ROHFP_[1--4]
ROH_CLK_[1--4] ROW_CLK_[1--4] RSD_CLK_[1--4] RLD_CLK_[1--4]
TRST_N
TDO
TDI
PM_CLK
TEA_N
INT_N
PCLK
TA_N
MPMODE
5-7952.f (F)
Figure 1. TSOT0410G4 Block Diagram, STS-192 Mode Agere Systems Inc. 13
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Description (continued)
TLDCC_[1--4] TOHDAT_[1--4]_[1:0]
TOH_CLK_[1--4] TOW_CLK_[1--4] TSD_CLK_[1--4] TLD_CLK_[1--4]
ADDRESS_[15:0]
TLCLOW_[1--4] TEXPOW_[1--4]
TSUSER_[1--4] TSDCC_[1--4]
TOHEN_[1--4] TOHFP_[1--4]
PARITY_[1:0]
DATA_[15:0]
TFRM T_CLK TD_1_[3:0] TD_2_[3:0] TD_3_[3:0] TD_4_[3:0] T_CLKO_[1--4] X4 STS_MODE = 1 R_CLK_[1--4] SECTION TRACE BUFFER X4 RECEIVE STS-48 RECEIVE STS-48 TRANSPORT OVERHEAD LINE PROCESSOR INTERFACE RECEIVE PATH OVERHEAD PROCESSOR RECEIVE DROP ALIGNER X4 PATH TRACE BUFFER STS PATH PROCESSING BLOCK X4 RECEIVE PAYLOAD DROP INTERFACE DFRM D_CLK DDATA_[16:1] DCTL_[1--4] RDDCC_[16:1] RDDCK_[1--4] JTAG INTERFACE X4 TRANSMIT STS-48 TRANSMIT STS-48 TRANSPORT OVERHEAD LINE PROCESSOR INTERFACE MICROPROCESSOR INTERFACE RST_N X4 TRANSMIT PAYLOAD ADD INTERFACE HIZ_N TADCC_[16:1] TADCK ADATA_[16:1]
RD_1_[3:0] RD_2_[3:0] RD_3_[3:0] RD_4_[3:0] RFRM[1--4]
RECEIVE POINTER PROCESSOR
R_CLKO_[1--4]
DRPBYP
TMS
TCK
REXPOW_[1--4]
RSUSER_[1--4]
RSDCC_[1--4]
RLCLOW_[1--4]
RLDCC_[1--4]
ROHDAT_[1--4]_[1:0]
ROHFP_[1--4]
ROH_CLK_[1--4] ROW_CLK_[1--4] RSD_CLK_[1--4] RLD_CLK_[1--4]
TRST_N
TDO
TDI
PM_CLK
TEA_N
RW_N
INT_N
CS_N
DS_N
PCLK
TS_N
TA_N
MPMODE
5-7982.e (F)
Figure 2. TSOT0410G4 Block Diagram, STS-48 Mode
Glossary
This glossary is not intended to list standard SDH or SONET terminology; rather, it is intended to describe terms that may be specific to this device and/or may be unfamiliar to the reader.
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Persistency Bit--a register bit that indicates the raw alarm has been continuously present since the alarm was latched in the latched alarm register bit. (See the Persistency Registers section on page 96.) PM--performance monitoring. Indication of the presence of an alarm or condition during the last second as indicated by successive rising edges of the PM_CLK input. PM counters count the number of occurrences of a condition, and 1-bit PM indicates that a condition was present at some time during the last second.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Description (continued)
Receive Direction Overview
In the receive direction, the receive line interface can accept either a single STS-192 (STM-64) signal or four STS-48 (STM-16) signals, from optical-to-electrical modules, in 16-bit or 4-bit wide serial 622 MHz format. The receive line interface synchronizes to the frames in each data channel and rotates the data to frame and byte align it. The data may also be optionally descrambled. The aligned data is received by the receive transport overhead processor, and the section (regenerator section) and line (multiplex section) overhead are extracted. Most of the overhead is then either stored internally or provided on external serial outputs, except for the pointer bytes, which are passed to the receive pointer processor. The receive pointer processor interprets the pointer bytes and provides the SONET payload envelope (SPE) timing for the receive-path overhead processor and the receive-drop data aligner (pointer processor). The receive-path overhead processor extracts the path overhead and either stores it internally or processes it for alarms and performance statistics. The receive-drop data aligner then translates the data from the receive clock domain to the drop clock domain using a small elastic store and pointer adjustments to the data. The resulting aligned data is then converted to sixteen 1-bit wide serial 622 MHz streams by the receive payload drop interface and output along with SPE timing signals for use by a payload mapping device.
Transmit Direction Overview
In the transmit direction, the transmit payload add interface accepts sixteen 1-bit wide serial 622 MHz pseudo* STS-12 (STM-4) signals and recovers the clock for each. The resulting 16 clocks must be synchronous in frequency, but can be asynchronous in phase. Each clock is used to frame, byte align, descramble, and then write its associated data stream into a small buffer. The data is then read out of all 16 buffers using transmit clock (T_CLK) and transmit frame (TFRM) timing. The converted data is passed along to the transmit transport overhead processor which adds the appropriate section and line overhead. This overhead is either provided by internal configuration registers or external serial inputs, except for the pointer bytes, which are received in the add data. The resulting valid STS-192 (STM-64) or STS-48 (STM-16) data is then optionally scrambled, converted to one 16-bit wide or four 4-bit wide serial 622 MHz signals, and output for use by electrical-to-optical modules. Transmit frame alignment synchronization may optionally be derived from any one of the 16 (selectable) add inputs. A software provisioning option allows transmit frame alignment synchronization to be provided using the timing that is being recovered from one of the add pseudo STS-12 links as the transmit frame sync instead of TFRM.
* The data is formatted as an STS-12 signal; however, most of the transport overhead bytes are either unused or may be used for proprietary purposes.
Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Description (continued)
STS-192 Mode Options
TOH Transparency In applications where it is desired, a pass-through capability using software provisioning for the TOH on the line interface to/from the TOH on the equipment interface is provided for the receive and transmit direction. This feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. On the receive side, when TOH transparency is enabled, the pointer generators and elastic stores in all path processing blocks are bypassed. In this case, receive timing will be used by the payload drop interface. The receive direction has the option for full TOH transparency, or just line overhead transparency with section overhead is used for the normal proprietary drop I/F overhead. When TOH transparency is enabled, the pointer processor (PP) will be bypassed on a per STS-48 level. See the Receive Pointer Processor section on page 62 for more information on how this mode effects the device. The transmit direction has the option for full TOH transparency or just line overhead (MSOH) transparency with section (RSOH) overhead inserted. If enabled, AIS insertion due to an E1/F1 code in the add TOH will be disabled. Regenerator Loopback In applications where the receive data and overhead bytes need to be transmitted towards the transmit line interface, a software regenerator loopback provisioning option is provided. To use this feature, the transmit clock must be derived from the receive clock at the 622 MHz level external to the device. The add interface buffers align the data between the receive and transmit clock domains. This mode will only function correctly when the device is in STS-192 mode. It will not work in STS-48 mode since the four STS-48 streams need to be aligned through the transmit side. Four received STS-48 streams are unlikely to be aligned to the same clock and frame alignment. The appropriate per STS-48 transmit line AIS insert control will be active during receive LOS, receive LOF, or R_CLK failure while in regenerator loopback.
Device Mode Setup
The basic operating mode of the TSOT0410G4 is set using external pins. The device can operate as a single STS-192 channel or as four separate STS-48 channels. The STS_MODE pin (AM17) determines which mode is used. Pulling the STS_MODE pin down to VSS selects STS-192 mode. In applications where no rate adaptation is required or desired, the pointer generators and elastic stores in all path processing blocks can be bypassed by pulling up the DRPBYP pin (AP11) to VDD. In this case, receive timing will be used by the payload drop interface. This mode should only be used if the device is in STS-192 mode. See the Receive Pointer Processor section on page 62 for more information on how this mode affects the device. The microprocessor interface can be set up to be synchronous by pulling up the MPMODE pin (E14) to VDD, or asynchronous by pulling down the pin to VSS. See the Microprocessor Interface section on page 93 for more information. For normal device operation, the TRST_N pin (AP30) should be tied low (to VSS). If TRST_N is high, a TCK clock must be present.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 Signal Name VDD VDD VSS VSS VDD2 VDD2 VSS VSS DATA_15 DATA_10 DATA_6 DATA_1 VSS CS_N ADDRESS_2 VSS VDD VDD ADDRESS_14 VSS TLD_CLK_4 TOH_CLK_4 VSS TSDCC_3 TOHFP_3 TSD_CLK_2 TSDCC_2 VSS VSS VDD2 VDD2 VSS VSS VDD VDD Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 Signal Name VDD VDD VSS VSS TADCC_14 TADCC_10 TADCC_6 TADCC_2 PARITY_1 DATA_11 DATA_7 DATA_2 TA_N RW_N ADDRESS_1 ADDRESS_5 ADDRESS_9 ADDRESS_13 TSUSER_4 TLDCC_4 TSD_CLK_4 TOHFP_4 TOW_CLK_3 TOHDAT_3_0 TLCLOW_2 TEXPOW_2 TOHDAT_2_0 TOH_CLK_2 TSUSER_1 TSD_CLK_1 TOHDAT_1_1 VSS VSS VDD VDD Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 Signal Name VSS VSS VDD VSS TADCC_15 TADCC_11 TADCC_7 TADCC_3 PARITY_0 DATA_12 DATA_8 DATA_3 TEA_N PCLK ADDRESS_0 ADDRESS_4 ADDRESS_8 ADDRESS_10 ADDRESS_15 TSDCC_4 TOHDAT_4_0 TLCLOW_3 TLD_CLK_3 TOHDAT_3_1 TOW_CLK_2 TSUSER_2 TOHDAT_2_1 TOHFP_2 TLDCC_1 TLD_CLK_1 TOHEN_1 VSS VDD VSS VSS Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 Signal Name VSS VSS VSS VDD2 TADCC_16 TADCC_12 TADCC_8 TADCC_4 TADCK DATA_13 DATA_9 DATA_4 INT_N PM_CLK DS_N ADDRESS_3 ADDRESS_7 ADDRESS_12 TEXPOW_4 TOW_CLK_4 TOHEN_4 TSUSER_3 TSD_CLK_3 TOHEN_3 TLD_CLK_2 NC TOHEN_2 TLCLOW_1 TSDCC_1 TOH_CLK_1 TOHFP_1 VDD2 VSS VSS VSS
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 Signal Name VDD2 ADATA_16 ADATA_16N CTAP_ADD4 VDD2 TADCC_13 TADCC_9 TADCC_5 TADCC_1 DATA_14 VDD DATA_5 DATA_0 MPMODE TS_N VDD2 ADDRESS_6 ADDRESS_11 TLCLOW_4 VDD2 TOHDAT_4_1 TEXPOW_3 TLDCC_3 TOH_CLK_3 VDD TLDCC_2 NC TEXPOW_1 TOW_CLK_1 TOHDAT_1_0 VDD2 T_CLK T_CLKN CTAP_TCLK VDD2 Pin F1 F2 F3 F4 F5 F31 F32 F33 F34 F35 G1 G2 G3 G4 G5 G31 G32 G33 G34 G35 H1 H2 H3 H4 H5 H31 H32 H33 H34 H35 J1 J2 J3 J4 J5 Signal Name VDD2 ADATA_14 ADATA_14N ADATA_15 ADATA_15N TFRM TFRMN T_CLKO_4 T_CLKO_4N VDD2 VSS REXT_ADD NC ADATA_13 ADATA_13N CTAP_TFRM TD15/TD_4_3 TD15N/TD_4_3N TD14/TD_4_2 VSS VSS ADATA_12 ADATA_12N NC CTAP_ADD3 TD14N/ TD_4_2N TD13/TD_4_1 TD13N/ TD_4_1N TD12/TD_4_0 VSS NC ADATA_11 ADATA_11N VDDA VSSA Pin J31 J32 J33 J34 J35 K1 K2 K3 K4 K5 K31 K32 K33 K34 K35 L1 L2 L3 L4 L5 L31 L32 L33 L34 L35 M1 M2 M3 M4 M5 M31 M32 M33 M34 M35 Signal Name TD12N/TD_4_0N T_CLKO_3 T_CLKO_3N TD11/TD_3_3 TD11N/TD_3_3N ADATA_9 ADATA_9N NC ADATA_10 ADATA_10N NC TD10/TD_3_2 TD10N/TD_3_2N TD9/TD_3_1 TD9N/TD_3_1N ADATA_8 ADATA_8N NC CTAP_ADD2 VDD VDD TD8/TD_3_0 TD8N/TD_3_0N T_CLKO_2 T_CLKO_2N CTAP_ADD1 ADATA_6 ADATA_6N ADATA_7 ADATA_7N TD7/TD_2_3 TD7N/TD_2_3N NC TD6/TD_2_2 TD6N/TD_2_2N Pin N1 N2 N3 N4 N5 N31 N32 N33 N34 N35 P1 P2 P3 P4 P5 P31 P32 P33 P34 P35 R1 R2 R3 R4 R5 R31 R32 R33 R34 R35 T1 T2 T3 T4 T5 Signal Name VSS NC ADATA_5 ADATA_5N NC TD5/TD_2_1 TD5N/ TD_2_1N TD4/TD_2_0 TD4N/ TD_2_0N VSS ADATA_3 ADATA_3N ADATA_4 NC ADATA_4N T_CLKO_1 T_CLKO_1N TD3/TD_1_3 TD3N/ TD_1_3N TD2/TD_1_2 ADATA_1 ADATA_1N NC ADATA_2 ADATA_2N TD2N/ TD_1_2N TD1/TD_1_1 TD1N/ TD_1_1N TD0/TD_1_0 TD0N/ TD_1_0N VSS VDDA VSSA NC VDD2
Note: NC refers to no connect. Do not connect pins so designated.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin T31 T32 T33 T34 T35 U1 U2 U3 U4 U5 U31 U32 U33 U34 U35 V1 V2 V3 V4 V5 V31 V32 V33 V34 V35 W1 W2 W3 W4 W5 W31 W32 W33 W34 W35 Signal Name VDD2 NC R_CLKO_1N R_CLKO_1 VSS DDATA_1 NC NC DCTL_1 DCTL_1N NC RFRM_1N RFRM_1 R_CLKO_2N VDD VDD DDATA_1N REXT_DRP1 DDATA_2 DDATA_2N RFRM_2N RFRM_2 R_CLKO_2 R_CLKO_3N VDD VDD DDATA_3 DDATA_3N DDATA_4 DDATA_4N RFRM_3 R_CLKO_4N RFRM_3N R_CLKO_4 R_CLKO_3 Pin Y1 Y2 Y3 Y4 Y5 Y31 Y32 Signal Name VSS NC VSSA VDDA VDD2 VDD2 CTAP_RCLK1 Pin AC31 AC32 AC33 AC34 AC35 AD1 AD2 Signal Name R_CLK_2 R_CLK_2N CTAP_RCLK2 RD3/RD_1_3 VSS VSSA VDDA Pin AG1 AG2 AG3 AG4 AG5 AG31 AG32 AG33 AG34 AG35 AH1 AH2 AH3 AH4 AH5 AH31 AH32 AH33 AH34 AH35 AJ1 AJ2 AJ3 AJ4 AJ5 AJ31 AJ32 AJ33 AJ34 AJ35 AK1 AK2 AK3 AK4 AK5 Signal Name NC DCTL_4 DCTL_4N DDATA_13 DDATA_13N RD10/RD_3_2 RD10N/ RD_3_2N RD9/RD_3_1 RD9N/RD_3_1N CTAP_RD3 VSS VSSA VDDA DDATA_14 DDATA_14N CTAP_RCLK4 RD11/RD_3_3 RD11N/ RD_3_3N NC VSS VSS NC REXT_DRP4 DDATA_15 DDATA_15N RD12/RD_4_0 RD12N/ RD_4_0N R_CLK_4 R_CLK_4N VSS VDD2 DDATA_16 DDATA_16N NC REF10E
Y33 RFRM_4 Y34 RFRM_4N Y35 VSS AA1 DCTL_2 AA2 DCTL_2N AA3 DDATA_5 AA4 DDATA_5N AA5 REXT_DRP2 AA31 RD0N/RD_1_0N AA32 RD0/RD_1_0 AA33 CTAP_RD1 AA34 R_CLK_1 AA35 R_CLK_1N AB1 NC AB2 DDATA_6 AB3 DDATA_6N AB4 DDATA_7 AB5 DDATA_7N AB31 RD2/RD_1_2 AB32 RD3N/RD_1_3N AB33 RD2N/RD_1_2N AB34 RD1/RD_1_1 AB35 RD1N/RD_1_1N AC1 VSS AC2 NC AC3 DDATA_8 AC4 DDATA_8N AC5 NC
AD3 DCTL_3 AD4 DCTL_3N AD5 REXT_DRP3 AD31 RD5/RD_2_1 AD32 RD5N/RD_2_1N AD33 RD4/RD_2_0 AD34 RD4N/RD_2_0N AD35 CTAP_RD2 AE1 DDATA_9 AE2 DDATA_9N AE3 DDATA_10 AE4 DDATA_10N AE5 VDD AE31 VDD AE32 RD7/RD_2_3 AE33 RD7N/RD_2_3N AE34 RD6/RD_2_2 AE35 RD6N/RD_2_2N AF1 NC AF2 DDATA_11 AF3 DDATA_11N AF4 DDATA_12 AF5 DDATA_12N AF31 RD8/RD_3_0 AF32 RD8N/RD_3_0N AF33 R_CLK_3 AF34 R_CLK_3N AF35 CTAP_RCLK3
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin Signal Name Pin Signal Name Pin AM31 AM32 AM33 AM34 AM35 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 Signal Name RESLOL VDD2 VSS VSS VSS VSS VSS VDD VSS PULLDN PULLDN PULLDN NC NC PULLDN D_CLK RDDCC_13 RDDCC_9 RDDCC_6 RDDCC_2 PULLUP RSD_CLK_4 ROHDAT_4_1 RLD_CLK_4 RSUSER_3 ROH_CLK_3 RLDCC_3 RSD_CLK_2 ROHDAT_2_1 REXPOW_2 ROW_CLK_1 RLD_CLK_1 PULLDN NC TMS Pin AN31 AN32 AN33 AN34 AN35 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 Signal Name RESHIL VSS VDD VSS VSS VDD VDD VSS VSS PULLDN PULLUP PULLDN NC NC PULLDN DRPBYP RDDCK_4 RDDCK_3 RDDCC_5 RDDCC_1 RST_N HIZ_N ROW_CLK_4 ROHDAT_4_0 REXPOW_4 ROW_CLK_3 RLD_CLK_3 RSUSER_2 ROHFP_2 RLCLOW_2 RSDCC_1 ROHDAT_1_0 REXPOW_1 PULLDN TRST_N
AK31 RD14/RD_4_2 AK32 RD14N/RD_4_2N AK33 RD13/RD_4_1 AK34 RD13N/RD_4_1N AK35 VDD2 AL1 VDD2 AL2 REF14E AL3 RESHIE AL4 RESLOE AL5 VDD2 AL6 PULLDN AL7 PULLUP AL8 NC AL9 NC AL10 PULLDN AL11 VDD AL12 RDDCC_15 AL13 RDDCC_11 AL14 RDDCC_7 AL15 RDDCC_3 AL16 VDD2 AL17 RSUSER_4 AL18 ROHFP_4 AL19 RLCLOW_4 AL20 VDD2 AL21 ROHDAT_3_1 AL22 REXPOW_3 AL23 ROW_CLK_2 AL24 RLD_CLK_2 AL25 VDD AL26 ROHFP_1 AL27 RLCLOW_1 AL28 PULLDN AL29 TDI AL30 REF10L
AL31 VDD2 AL32 RD15/RD_4_3 AL33 RD15N/RD_4_3N AL34 CTAP_RD4 AL35 VDD2 AM1 VSS AM2 VSS AM3 VSS AM4 VDD2 AM5 PULLDN AM6 PULLDN AM7 PULLDN AM8 NC AM9 NC AM10 PULLDN AM11 DFRM AM12 RDDCC_14 AM13 RDDCC_10 AM14 RDDCC_8 AM15 RDDCC_4 AM16 PULLUP AM17 STS_MODE AM18 ROH_CLK_4 AM19 RLDCC_4 AM20 RSD_CLK_3 AM21 ROHFP_3 AM22 RLCLOW_3 AM23 RSDCC_2 AM24 ROHDAT_2_0 AM25 RSUSER_1 AM26 ROH_CLK_1 AM27 RLDCC_1 AM28 PULLDN AM29 TCK AM30 TDO
Note: NC refers to no connect. Do not connect pins so designated.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Pin AP31 AP32 AP33 AP34 AP35 AR1 AR2 AR3 AR4 AR5 Signal Name REF14L VSS VSS VDD VDD VDD VDD VSS VSS VDD2 Pin AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 Signal Name VDD2 VSS VSS NC PULLDN RDDCC_16 RDDCC_12 VSS RDDCK_2 RDDCK_1 Pin AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 Signal Name VSS RSDCC_4 VDD VDD VSS RSDCC_3 ROHDAT_3_0 VSS ROH_CLK_2 RLDCC_2 Pin AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 Signal Name RSD_CLK_1 ROHDAT_1_1 VSS VSS VDD2 VDD2 VSS VSS VDD VDD
Note: NC refers to no connect. Do not connect pins so designated.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order Pin R1 R2 R4 R5 P1 P2 P3 P5 N3 N4 M2 M3 M4 M5 L1 L2 K1 K2 K4 K5 J2 J3 H2 H3 G4 G5 F2 F3 F4 F5 E2 E3 C15 B15 A15 Signal Name ADATA_1 ADATA_1N ADATA_2 ADATA_2N ADATA_3 ADATA_3N ADATA_4 ADATA_4N ADATA_5 ADATA_5N ADATA_6 ADATA_6N ADATA_7 ADATA_7N ADATA_8 ADATA_8N ADATA_9 ADATA_9N ADATA_10 ADATA_10N ADATA_11 ADATA_11N ADATA_12 ADATA_12N ADATA_13 ADATA_13N ADATA_14 ADATA_14N ADATA_15 ADATA_15N ADATA_16 ADATA_16N ADDRESS_0 ADDRESS_1 ADDRESS_2 Pin D16 C16 B16 E17 D17 C17 B17 C18 E18 D18 B18 A19 C19 A14 M1 L4 H5 E4 Y32 AC33 AF35 AH31 AA33 AD35 AG35 AL34 E34 G31 AN11 E13 A12 B12 C12 D12 E12 Signal Name ADDRESS_3 ADDRESS_4 ADDRESS_5 ADDRESS_6 ADDRESS_7 ADDRESS_8 ADDRESS_9 ADDRESS_10 ADDRESS_11 ADDRESS_12 ADDRESS_13 ADDRESS_14 ADDRESS_15 CS_N CTAP_ADD1 CTAP_ADD2 CTAP_ADD3 CTAP_ADD4 CTAP_RCLK1 CTAP_RCLK2 CTAP_RCLK3 CTAP_RCLK4 CTAP_RD1 CTAP_RD2 CTAP_RD3 CTAP_RD4 CTAP_TCLK CTAP_TFRM D_CLK DATA_0 DATA_1 DATA_2 DATA_3 DATA_4 DATA_5 Pin A11 B11 C11 D11 A10 B10 C10 D10 E10 A9 U4 U5 AA1 AA2 AD3 AD4 AG2 AG3 U1 V2 V4 V5 W2 W3 W4 W5 AA3 AA4 AB2 AB3 AB4 AB5 AC3 AC4 AE1 Signal Name DATA_6 DATA_7 DATA_8 DATA_9 DATA_10 DATA_11 DATA_12 DATA_13 DATA_14 DATA_15 DCTL_1 DCTL_1N DCTL_2 DCTL_2N DCTL_3 DCTL_3N DCTL_4 DCTL_4N DDATA_1 DDATA_1N DDATA_2 DDATA_2N DDATA_3 DDATA_3N DDATA_4 DDATA_4N DDATA_5 DDATA_5N DDATA_6 DDATA_6N DDATA_7 DDATA_7N DDATA_8 DDATA_8N DDATA_9 Pin AE2 AE3 AE4 AF2 AF3 AF4 AF5 AG4 AG5 AH4 AH5 AJ4 AJ5 AK2 AK3 AM11 AP11 D15 AP17 D13 E14 D26 E27 G3 H4 J1 K3 K31 L3 M33 N2 N5 P4 R3 T4 Signal Name DDATA_9N DDATA_10 DDATA_10N DDATA_11 DDATA_11N DDATA_12 DDATA_12N DDATA_13 DDATA_13N DDATA_14 DDATA_14N DDATA_15 DDATA_15N DDATA_16 DDATA_16N DFRM DRPBYP DS_N HIZ_N INT_N MPMODE NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Note: NC refers to no connect. Do not connect pins so designated.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued) Pin T32 U2 U3 U31 Y2 AB1 AC2 AC5 AF1 AG1 AH34 AJ2 AK4 AL8 AL9 AM8 AM9 AN8 AN9 AN29 AP8 AP9 AR9 C9 B9 C14 D14 AL6 AL10 AL28 AM5 AM6 AM7 AM10 AM28 Signal Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PARITY_0 PARITY_1 PCLK PM_CLK PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN Pin AN5 AN6 AN7 AN10 AN28 AP5 AP7 AP10 AP29 AR10 AL7 AP6 AM16 AN16 AA34 AA35 AC31 AC32 AF33 AF34 AJ33 AJ34 T34 T33 V33 U34 W35 V34 W34 W32 AA32 AA31 AB34 AB35 AB31 Signal Name PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLDN PULLUP PULLUP PULLUP PULLUP R_CLK_1 R_CLK_1N R_CLK_2 R_CLK_2N R_CLK_3 R_CLK_3N R_CLK_4 R_CLK_4N R_CLKO_1 R_CLKO_1N R_CLKO_2 R_CLKO_2N R_CLKO_3 R_CLKO_3N R_CLKO_4 R_CLKO_4N RD0/RD_1_0 RD0N/RD_1_0N RD1/RD_1_1 RD1N/RD_1_1N RD2/RD_1_2 Pin AB33 AC34 AB32 AD33 AD34 AD31 AD32 AE34 AE35 AE32 AE33 AF31 AF32 AG33 AG34 AG31 AH32 AJ31 AK33 AK31 AL32 AP15 AN15 AL15 AM15 AP14 AN14 AL14 AM14 Signal Name RD2N/RD_1_2N RD3/RD_1_3 RD3N/RD_1_3N RD4/RD_2_0 RD4N/RD_2_0N RD5/RD_2_1 RD5N/RD_2_1N RD6/RD_2_2 RD6N/RD_2_2N RD7/RD_2_3 RD7N/RD_2_3N RD8/RD_3_0 RD8N/RD_3_0N RD9/RD_3_1 RD9N/RD_3_1N RD10/RD_3_2 RD11/RD_3_3 RD12/RD_4_0 RD13/RD_4_1 RD14/RD_4_2 RD15/RD_4_3 RDDCC_1 RDDCC_2 RDDCC_3 RDDCC_4 RDDCC_5 RDDCC_6 RDDCC_7 RDDCC_8 Pin AN13 AM13 AL13 AR12 AN12 AM12 AL12 AR11 AR15 AR14 AP13 AP12 AK5 AL30 AL2 AP31 AL3 AN31 AL4 AM31 AP28 AN25 AL22 AP20 G2 V3 AA5 AD5 AJ3 U33 U32 V32 V31 W31 W33 Signal Name RDDCC_9 RDDCC_10 RDDCC_11 RDDCC_12 RDDCC_13 RDDCC_14 RDDCC_15 RDDCC_16 RDDCK_1 RDDCK_2 RDDCK_3 RDDCK_4 REF10E REF10L REF14E REF14L RESHIE RESHIL RESLOE RESLOL REXPOW_1 REXPOW_2 REXPOW_3 REXPOW_4 REXT_ADD REXT_DRP1 REXT_DRP2 REXT_DRP3 REXT_DRP4 RFRM_1 RFRM_1N RFRM_2 RFRM_2N RFRM_3 RFRM_3N
AG32 RD10N/RD_3_2N AH33 RD11N/RD_3_3N AJ32 RD12N/RD_4_0N AK34 RD13N/RD_4_1N AK32 RD14N/RD_4_2N AL33 RD15N/RD_4_3N
Note: NC refers to no connect. Do not connect pins so designated.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued) Pin Y33 Y34 AL27 AP25 AM22 AL19 AN27 AL24 AP22 AN19 AM27 AR25 AN22 AM19 AM26 AR24 AN21 AM18 AP27 AR27 AN24 AR22 AL21 AP19 AN18 AL26 AP24 AM21 AL18 AN26 AL23 AP21 AP18 AR26 Signal Name RFRM_4 RFRM_4N RLCLOW_1 RLCLOW_2 RLCLOW_3 RLCLOW_4 RLD_CLK_1 RLD_CLK_2 RLD_CLK_3 RLD_CLK_4 RLDCC_1 RLDCC_2 RLDCC_3 RLDCC_4 ROH_CLK_1 ROH_CLK_2 ROH_CLK_3 ROH_CLK_4 ROHDAT_1_0 ROHDAT_1_1 ROHDAT_2_1 ROHDAT_3_0 ROHDAT_3_1 ROHDAT_4_0 ROHDAT_4_1 ROHFP_1 ROHFP_2 ROHFP_3 ROHFP_4 ROW_CLK_1 ROW_CLK_2 ROW_CLK_3 ROW_CLK_4 RSD_CLK_1 Pin AN23 AM20 AN17 AP26 AM23 AR21 AR17 AP16 AM25 AP23 AN20 AL17 B14 AM17 E32 E33 P31 P32 L34 L35 J32 J33 F33 F34 B13 E9 B8 C8 D8 E8 B7 C7 D7 E7 B6 Signal Name RSD_CLK_2 RSD_CLK_3 RSD_CLK_4 RSDCC_1 RSDCC_2 RSDCC_3 RSDCC_4 RST_N RSUSER_1 RSUSER_2 RSUSER_3 RSUSER_4 RW_N STS_MODE T_CLK T_CLKN T_CLKO_1 T_CLKO_1N T_CLKO_2 T_CLKO_2N T_CLKO_3 T_CLKO_3N T_CLKO_4 T_CLKO_4N TA_N TADCC_1 TADCC_2 TADCC_3 TADCC_4 TADCC_5 TADCC_6 TADCC_7 TADCC_8 TADCC_9 TADCC_10 Pin C6 D6 E6 B5 C5 D5 D9 AM29 R34 R35 R32 R33 P35 R31 P33 P34 N33 N34 N31 N32 M34 M35 M31 M32 L32 L33 K34 K35 K32 K33 J34 J35 H34 J31 H32 Signal Name TADCC_11 TADCC_12 TADCC_13 TADCC_14 TADCC_15 TADCC_16 TADCK TCK TD0/TD_1_0 TD0N/TD_1_0N TD1/TD_1_1 TD1N/TD_1_1N TD2/TD_1_2 TD2N/TD_1_2N TD3/TD_1_3 TD3N/TD_1_3N TD4/TD_2_0 TD4N/TD_2_0N TD5/TD_2_1 TD5N/TD_2_1N TD6/TD_2_2 TD6N/TD_2_2N TD7/TD_2_3 TD7N/TD_2_3N TD8/TD_3_0 TD8N/TD_3_0N TD9/TD_3_1 TD9N/TD_3_1N TD10/TD_3_2 TD10N/TD_3_2N TD11/TD_3_3 TD11N/TD_3_3N TD12/TD_4_0 TD12N/TD_4_0N TD13/TD_4_1 Pin H33 G34 H31 G32 G33 AL29 AM30 C13 E28 B26 E22 D19 F31 F32 D28 B25 C22 E19 C30 D25 C23 A21 C29 E26 E23 B20 AN30 D30 B28 E24 A22 E30 B31 B27 C27 Signal Name TD13N/TD_4_1N TD14/TD_4_2 TD14N/TD_4_2N TD15/TD_4_3 TD15N/TD_4_3N TDI TDO TEA_N TEXPOW_1 TEXPOW_2 TEXPOW_3 TEXPOW_4 TFRM TFRMN TLCLOW_1 TLCLOW_2 TLCLOW_3 TLCLOW_4 TLD_CLK_1 TLD_CLK_2 TLD_CLK_3 TLD_CLK_4 TLDCC_1 TLDCC_2 TLDCC_3 TLDCC_4 TMS TOH_CLK_1 TOH_CLK_2 TOH_CLK_3 TOH_CLK_4 TOHDAT_1_0 TOHDAT_1_1 TOHDAT_2_0 TOHDAT_2_1
AM24 ROHDAT_2_0
Note: NC refers to no connect. Do not connect pins so designated.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued) Pin B24 C24 C21 E21 C31 D27 D24 D21 D31 C28 A25 B22 E29 C25 B23 D20 AP30 E15 B30 A26 D23 B21 D29 A27 A24 C20 B29 C26 D22 B19 A1 A2 A17 A18 A34 Signal Name TOHDAT_3_0 TOHDAT_3_1 TOHDAT_4_0 TOHDAT_4_1 TOHEN_1 TOHEN_2 TOHEN_3 TOHEN_4 TOHFP_1 TOHFP_2 TOHFP_3 TOHFP_4 TOW_CLK_1 TOW_CLK_2 TOW_CLK_3 TOW_CLK_4 TRST_N TS_N TSD_CLK_1 TSD_CLK_2 TSD_CLK_3 TSD_CLK_4 TSDCC_1 TSDCC_2 TSDCC_3 TSDCC_4 TSUSER_1 TSUSER_2 TSUSER_3 TSUSER_4 VDD VDD VDD VDD VDD Pin A35 B1 B2 B34 B35 C3 C33 E11 E25 L5 L31 U35 V1 V35 W1 AE5 AE31 AL11 AL25 AN3 AN33 AP1 AP2 AP34 AP35 AR1 AR2 AR18 AR19 AR34 AR35 A5 A6 A30 A31 Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2 Pin D4 D32 E1 E5 E16 E20 E31 E35 F1 F35 T5 T31 Y5 Y31 AK1 AK35 AL1 AL5 AL16 AL20 AL31 AL35 AM4 AM32 AR5 AR6 AR30 AR31 J4 T2 Y4 AD2 AH3 A3 A4 Signal Name VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDDA VDDA VDDA VDDA VDDA VSS VSS Pin A7 A8 A13 A16 A20 A23 A28 A29 A32 A33 B3 B4 B32 B33 C1 C2 C4 C32 C34 C35 D1 D2 D3 D33 D34 D35 G1 G35 H1 H35 N1 N35 T1 T35 Y1 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Note: NC refers to no connect. Do not connect pins so designated.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued) Pin Y35 AC1 AC35 AH1 AH35 AJ1 AJ35 AM1 AM2 AM3 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AM33 AM34 AM35 AN1 AN2 AN4 AN32 AN34 AN35 AP3 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AP4 AP32 AP33 AR3 AR4 AR7 AR8 AR13 AR16 AR20 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AR23 AR28 AR29 AR32 AR33 J5 T3 Y3 AD1 AH2 Signal Name VSS VSS VSS VSS VSS VSSA VSSA VSSA VSSA VSSA
Note: NC refers to no connect. Do not connect pins so designated.
Table 3. Pin Descriptions--System Control Pin AP17 Symbol HIZ_N Type1 I
u
Name/Description Global Pin 3-State Control (Active-Low). This input incorporates a Schmitt trigger. The minimum hysteresis is 0.3 V. Setting this input to 0 causes all TSOT0410G4 outputs to assume a high-impedance state except for the JTAG test data output (TDO) pin. Asynchronous Chip Reset (Active-Low). This input incorporates a Schmitt trigger. The minimum hysteresis is 0.3 V. Setting this input to 0 causes an asynchronous reset of the device. To ensure proper reset, this input should be held low for a minimum of 26 ns (at least two 77.76 MHz clock cycles). STS Mode Select. See the Device Mode Setup section on page 16 for details. 1 = STS-48. 0 = STS-192. Pointer Generator Bypass Enable. See Pointer Generator Functions on page 65 for details. 1 = Bypass. 0 = Enable pointer generator. Microprocessor Mode. See the Microprocessor Interface section on page 93 for details. 1 = Synchronous mode. 0 = Asynchronous mode. One Second Performance Monitoring Clock. The performance monitoring registers are updated on the rising edge of this signal. The internal PM anomaly counters are cleared at the same time. PM_CLK must be high for at least 26 ns, and low for at least 26 ns. The period of the performance monitoring clock will normally be 1 s, but the minimum period required for proper operation is 325 ns (during testing and development, for example).
AP16
RST_N
Iu
AM17
STS_MODE
Id
AP11
DRPBYP
Id
E14
MPMODE
Iu
D14
PM_CLK
I
1. I = input, Id = input with internal pull-down resistor, Iu = input with internal pull-up resistor. The value of all internal pull-up/pull-down resistors is 50 k. All I/Os in Table 3 are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 4. Pin Descriptions--Receive Line Interface Pin AA34 AA35 T34 T33 AA32 AA31 AB34 AB35 AB31 AB33 AC34 AB32 U33 U32 AC31 AC32 V33 U34 AD33 AD34 AD31 AD32 AE34 AE35 AE32 AE33 V32 V31 AF33 AF34 W35 V34 AF31 AF32 AG33 AG34 STS-192 Symbol R_CLK_1 R_CLK_1N R_CLKO_1 R_CLKO_1N RD0 RD0N RD1 RD1N RD2 RD2N RD3 RD3N RFRM_1 RFRM_1N R_CLK_2 R_CLK_2N R_CLKO_2 R_CLKO_2N RD4 RD4N RD5 RD5N RD6 RD6N RD7 RD7N RFRM_1 RFRM_1N R_CLK_3 R_CLK_3N R_CLKO_3 R_CLKO_3N RD8 RD8N RD9 RD9N STS-48 Symbol R_CLK_1 R_CLK_1N R_CLKO_1 R_CLKO_1N RD_1_0 RD_1_0N RD_1_1 RD_1_1N RD_1_2 RD_1_2N RD_1_3 RD_1_3N RFRM_1 RFRM_1N R_CLK_2 R_CLK_2N R_CLKO_2 R_CLKO_2N RD_2_0 RD_2_0N RD_2_1 RD_2_1N RD_2_2 RD_2_2N RD_2_3 RD_2_3N RFRM_1 RFRM_1N R_CLK_3 R_CLK_3N R_CLKO_3 R_CLKO_3N RD_3_0 RD_3_0N RD_3_1 RD_3_1N Type 1 I LVDS O LVDS I LVDS I LVDS I LVDS I LVDS O LVDS I LVDS O LVDS I LVDS I LVDS I LVDS I LVDS O LVDS I LVDS O LVDS I LVDS I LVDS Name/Description STS_MODE = 1: STS-48 receive channel 1 clock (622 MHz). STS_MODE = 0: STS-192 receive channel 1 clock (622 MHz). Receive Clock 1 Loopback. STS_MODE = 1: STS-48 clock loopback output for channel 1. STS_MODE = 0: STS-192 clock loopback. STS_MODE = 1: STS-48 receive channel 1 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 0 (LSB). STS_MODE = 1: STS-48 receive channel 1 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 1. STS_MODE = 1: STS-48 receive channel 1 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 2. STS_MODE = 1: STS-48 receive channel 1 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 3. STS_MODE = 1: STS-48 receive channel 1 frame sync. STS_MODE = 0: STS-192 receive channel 1 frame sync. STS_MODE = 1: STS-48 receive channel 2 clock (622 MHz). STS_MODE = 0: Not used. Receive Clock 2 Loopback. STS_MODE = 1: STS-48 clock loopback output for channel 2. STS_MODE = 0: Copy of receive clock 1 loopback. STS_MODE = 1: STS-48 receive channel 2 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 4. STS_MODE = 1: STS-48 receive channel 2 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 5. STS_MODE = 1: STS-48 receive channel 2 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 6. STS_MODE = 1: STS-48 receive channel 2 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 7. STS_MODE = 1: STS-48 receive channel 2 frame sync. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 clock (622 MHz). STS_MODE = 0: Not used. Receive Clock 3 Loopback. STS_MODE = 1: STS-48 clock loopback output for channel 3. STS_MODE = 0: Copy of receive clock 1 loopback. STS_MODE = 1: STS-48 receive channel 3 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 8. STS_MODE = 1: STS-48 receive channel 3 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 9.
1. I = input, O = output, LVDS = low-voltage differential signal.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 4. Pin Descriptions--Receive Line Interface (continued) Pin AG31 AG32 AH32 AH33 W31 W33 AJ33 AJ34 W34 W32 AJ31 AJ32 AK33 AK34 AK31 AK32 AL32 AL33 Y33 Y34 STS-192 Symbol RD10 RD10N RD11 RD11N RFRM_3 RFRM_3N R_CLK_4 R_CLK_4N R_CLKO_4 R_CLKO_4N RD12 RD12N RD13 RD13N RD14 RD14N RD15 RD15N RFRM_4 RFRM_4N STS-48 Symbol RD_3_2 RD_3_2N RD_3_3 RD_3_3N RFRM_3 RFRM_3N R_CLK_4 R_CLK_4N R_CLKO_4 R_CLKO_4N RD_4_0 RD_4_0N RD_4_1 RD_4_1N RD_4_2 RD_4_2N RD_4_3 RD_4_3N RFRM_4 RFRM_4N Type1 I LVDS I LVDS O LVDS I LVDS O LVDS I LVDS I LVDS I LVDS I LVDS O LVDS Name/Description STS_MODE = 1: STS-48 receive channel 3 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 10. STS_MODE = 1: STS-48 receive channel 3 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 11. STS_MODE = 1: STS-48 receive channel 3 frame sync. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 clock (622 MHz). STS_MODE = 0: Not used. Receive Clock 4 Loopback. STS_MODE = 1: STS-48 clock loopback output for channel 4. STS_MODE = 0: Copy of receive clock 1 loopback. STS_MODE = 1: STS-48 receive channel 4 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 12. STS_MODE = 1: STS-48 receive channel 4 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 13. STS_MODE = 1: STS-48 receive channel 4 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 14. STS_MODE = 1: STS-48 receive channel 4 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 15 (MSB). STS_MODE = 1: STS-48 receive channel 4 frame sync. STS_MODE = 0: Not used.
1. I = input, O = output, LVDS = low-voltage differential signal.
Table 5. Pin Descriptions--Transmit Line Interface Pin E32 E33 F31 F32 STS-192 Symbol T_CLK T_CLKN TFRM TFRMN STS-48 Symbol T_CLK T_CLKN TFRM TFRMN Type1 I LVDS I LVDS Name/Description Transmit Clock. 622 MHz clock input for all channels. This is the clock input to the entire transmit section. Transmit Frame Sync. Frame sync input for all channels. This signal is required for operation of the transmit section. TFRM must be low for at least 32 T_CLK clock periods and then stay high for at least 32 more T_CLK periods after the rising edge. See the Add Interface Framing (A1 and A2) section on page 82 for details. Transmit Clock 1 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 1. STS_MODE = 0: STS-192 transmit clock output. STS_MODE = 1: STS-48 transmit channel 1 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 0 (LSB).
P31 P32 R34 R35
T_CLKO_1 T_CLKO_1N TD0 TD0N
T_CLKO_1 T_CLKO_1N TD_1_0 TD_1_0N
O LVDS O LVDS
1. I = input, O = output, LVDS = low-voltage differential signal.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 5. Pin Descriptions--Transmit Line Interface (continued) Pin R32 R33 P35 R31 P33 P34 L34 L35 N33 N34 N31 N32 M34 M35 M31 M32 J32 J33 L32 L33 K34 K35 K32 K33 J34 J35 F33 F34 H34 J31 H32 H33 G34 H31 G32 G33 STS-192 Symbol TD1 TD1N TD2 TD2N TD3 TD3N T_CLKO_2 T_CLKO_2N TD4 TD4N TD5 TD5N TD6 TD6N TD7 TD7N T_CLKO_3 T_CLKO_3N TD8 TD8N TD9 TD9N TD10 TD10N TD11 TD11N T_CLKO_4 T_CLKO_4N TD12 TD12N TD13 TD13N TD14 TD14N TD15 TD15N STS-48 Symbol TD_1_1 TD_1_1N TD_1_2 TD_1_2N TD_1_3 TD_1_3N T_CLKO_2 T_CLKO_2N TD_2_0 TD_2_0N TD_2_1 TD_2_1N TD_2_2 TD_2_2N TD_2_3 TD_2_3N T_CLKO_3 T_CLKO_3N TD_3_0 TD_3_0N TD_3_1 TD_3_1N TD_3_2 TD_3_2N TD_3_3 TD_3_3N T_CLKO_4 T_CLKO_4N TD_4_0 TD_4_0N TD_4_1 TD_4_1N TD_4_2 TD_4_2N TD_4_3 TD_4_3N Type1 O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS Name/Description STS_MODE = 1: STS-48 transmit channel 1 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 1. STS_MODE = 1: STS-48 transmit channel 1 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 2. STS_MODE = 1: STS-48 transmit channel 1 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 3. Transmit Clock 2 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 2. STS_MODE = 0: Copy of transmit clock 1 loopback. STS_MODE = 1: STS-48 transmit channel 2 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 4. STS_MODE = 1: STS-48 transmit channel 2 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 5. STS_MODE = 1: STS-48 transmit channel 2 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 6. STS_MODE = 1: STS-48 transmit channel 2 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 7. Transmit Clock 3 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 3. STS_MODE = 0: Copy of transmit clock 1 loopback. STS_MODE = 1: STS-48 transmit channel 3 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 8. STS_MODE = 1: STS-48 transmit channel 3 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 9. STS_MODE = 1: STS-48 transmit channel 3 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 10. STS_MODE = 1: STS-48 transmit channel 3 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 11. Transmit Clock 4 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 4. STS_MODE = 0: Copy of transmit clock 1 loopback. STS_MODE = 1: STS-48 transmit channel 4 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 12. STS_MODE = 1: STS-48 transmit channel 4 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 13. STS_MODE = 1: STS-48 transmit channel 4 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 14. STS_MODE = 1: STS-48 transmit channel 4 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 15 (MSB).
1. O = output, LVDS = low-voltage differential signal.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 6. Pin Descriptions--LVDS Reference, Line Interface Pin AA33 Symbol CTAP_RD1 Type1 I LVDS Term I LVDS Term I LVDS Term I LVDS Term I LVDS Term I LVDS Term I LVDS Term I LVDS Term I LVDS Term I LVDS Term I I I I Name/Description Center Tap for RD_1 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for RD_2 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for RD_3 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for RD_4 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for R_CLK_1 Input. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for R_CLK_2 Input. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for R_CLK_3 Input. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for R_CLK_4 Input. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for T_CLK Input. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for TFRM Input. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. 1.0 V 3% reference voltage for line interface I/Os. An example circuit is shown in Figure 3 on page 35. 1.4 V 3% reference voltage for line interface I/Os. An example circuit is shown in Figure 3 on page 35. Connect a 100 1% resistor between these pins.
AD35
CTAP_RD2
AG35
CTAP_RD3
AL34
CTAP_RD4
Y32
CTAP_RCLK1
AC33
CTAP_RCLK2
AF35
CTAP_RCLK3
AH31
CTAP_RCLK4
E34
CTAP_TCLK
G31
CTAP_TFRM
AL30 AP31 AN31 AM31
REF10L REF14L RESHIL RESLOL
1. I = input. I LVDS term = low-voltage differential signal termination pin.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 7. Pin Descriptions--Receive Drop Equipment Interface Pin AN11 AM11 U1 V2 AP15 V4 V5 AN15 W2 W3 AL15 W4 W5 AM15 U4 U5 AR15 AA3 AA4 AP14 AB2 AB3 AN14 AB4 AB5 AL14 AC3 AC4 AM14 AA1 AA2 AR14 Symbol D_CLK DFRM DDATA_1 DDATA_1N RDDCC_1 DDATA_2 DDATA_2N RDDCC_2 DDATA_3 DDATA_3N RDDCC_3 DDATA_4 DDATA_4N RDDCC_4 DCTL_1 DCTL_1N RDDCK_1 DDATA_5 DDATA_5N RDDCC_5 DDATA_6 DDATA_6N RDDCC_6 DDATA_7 DDATA_7N RDDCC_7 DDATA_8 DDATA_8N RDDCC_8 DCTL_2 DCTL_2N RDDCK_2 Type1 I/O I/O O LVDS I O LVDS I O LVDS I O LVDS I O LVDS O O LVDS I O LVDS I O LVDS I O LVDS I O LVDS O Name/Description DRPBYP = 1: output: receive channel 1 clock (78 MHz). DRPBYP = 0: input: receive drop clock (78 MHz)--all channels. DRPBYP = 1: output: receive channel 1 frame sync. DRPBYP = 0: input: receive drop frame sync--all channels. Receive drop STS-12 channel 1 serial data (622 MHz). Receive drop STS-12 channel 1 section DCC serial link. Receive drop STS-12 channel 2 serial data (622 MHz). Receive drop STS-12 channel 2 section DCC serial link. Receive drop STS-12 channel 3 serial data (622 MHz). Receive drop STS-12 channel 3 section DCC serial link. Receive drop STS-12 channel 4 serial data (622 MHz). Receive drop STS-12 channel 4 section DCC serial link. Receive drop STS-12 channels 1--4 timing control (622 MHz). Receive drop STS-12 channels 1--4 section DCC clock. Receive drop STS-12 channel 5 serial data (622 MHz). Receive drop STS-12 channel 5 section DCC serial link. Receive drop STS-12 channel 6 serial data (622 MHz). Receive drop STS-12 channel 6 section DCC serial link. Receive drop STS-12 channel 7 serial data (622 MHz). Receive drop STS-12 channel 7 section DCC serial link. Receive drop STS-12 channel 8 serial data (622 MHz). Receive drop STS-12 channel 8 section DCC serial link. Receive drop STS-12 channels 5--8 timing control (622 MHz). Receive drop STS-12 channels 5--8 section DCC clock.
1. I = input, O = output, I/O = bidirectional pin, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 7. Pin Descriptions--Receive Drop Equipment Interface (continued) Pin AE1 AE2 AN13 AE3 AE4 AM13 AF2 AF3 AL13 AF4 AF5 AR12 AD3 AD4 AP13 AG4 AG5 AN12 AH4 AH5 AM12 AJ4 AJ5 AL12 AK2 AK3 AR11 AG2 AG3 AP12 Symbol DDATA_9 DDATA_9N RDDCC_9 DDATA_10 DDATA_10N RDDCC_10 DDATA_11 DDATA_11N RDDCC_11 DDATA_12 DDATA_12N RDDCC_12 DCTL_3 DCTL_3N RDDCK_3 DDATA_13 DDATA_13N RDDCC_13 DDATA_14 DDATA_14N RDDCC_14 DDATA_15 DDATA_15N RDDCC_15 DDATA_16 DDATA_16N RDDCC_16 DCTL_4 DCTL_4N RDDCK_4 Type1 O LVDS I O LVDS I O LVDS I O LVDS I O LVDS O O LVDS I O LVDS I O LVDS I O LVDS I O LVDS O Name/Description Receive drop STS-12 channel 9 serial data (622 MHz). Receive drop STS-12 channel 9 section DCC serial link. Receive drop STS-12 channel 10 serial data (622 MHz). Receive drop STS-12 channel 10 section DCC serial link. Receive drop STS-12 channel 11 serial data (622 MHz). Receive drop STS-12 channel 11 section DCC serial link. Receive drop STS-12 channel 12 serial data (622 MHz). Receive drop STS-12 channel 12 section DCC serial link. Receive drop STS-12 channels 9--12 timing control (622 MHz). Receive drop STS-12 channels 9--12 section DCC clock. Receive drop STS-12 channel 13 serial data (622 MHz). Receive drop STS-12 channel 13 section DCC serial link. Receive drop STS-12 channel 14 serial data (622 MHz). Receive drop STS-12 channel 14 section DCC serial link. Receive drop STS-12 channel 15 serial data (622 MHz). Receive drop STS-12 channel 15 section DCC serial link. Receive drop STS-12 channel 16 serial data (622 MHz). Receive drop STS-12 channel 16 section DCC serial link. Receive drop STS-12 channels 13--16 timing control (622 MHz). Receive drop STS-12 channels 13--16 section DCC clock.
1. I = input, O = output, I/O = bidirectional pin, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 8. Pin Descriptions--Transmit Add Equipment Interface Pin R1 R2 E9 R4 R5 B8 P1 P2 C8 P3 P5 D8 N3 N4 E8 M2 M3 B7 M4 M5 C7 L1 L2 D7 K1 K2 E7 K4 K5 B6 Symbol ADATA_1 ADATA_1N TADCC_1 ADATA_2 ADATA_2N TADCC_2 ADATA_3 ADATA_3N TADCC_3 ADATA_4 ADATA_4N TADCC_4 ADATA_5 ADATA_5N TADCC_5 ADATA_6 ADATA_6N TADCC_6 ADATA_7 ADATA_7N TADCC_7 ADATA_8 ADATA_8N TADCC_8 ADATA_9 ADATA_9N TADCC_9 ADATA_10 ADATA_10N TADCC_10 Type1 I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O Name/Description Transmit add STS-12 channel 1 serial data (622 MHz). Transmit add STS-12 channel 1 section DCC serial link. Transmit add STS-12 channel 2 serial data (622 MHz). Transmit add STS-12 channel 2 section DCC serial link. Transmit add STS-12 channel 3 serial data (622 MHz). Transmit add STS-12 channel 3 section DCC serial link. Transmit add STS-12 channel 4 serial data (622 MHz). Transmit add STS-12 channel 4 section DCC serial link. Transmit add STS-12 channel 5 serial data (622 MHz). Transmit add STS-12 channel 5 section DCC serial link. Transmit add STS-12 channel 6 serial data (622 MHz). Transmit add STS-12 channel 6 section DCC serial link. Transmit add STS-12 channel 7 serial data (622 MHz). Transmit add STS-12 channel 7 section DCC serial link. Transmit add STS-12 channel 8 serial data (622 MHz). Transmit add STS-12 channel 8 section DCC serial link. Transmit add STS-12 channel 9 serial data (622 MHz). Transmit add STS-12 channel 9 section DCC serial link. Transmit add STS-12 channel 10 serial data (622 MHz). Transmit add STS-12 channel 10 section DCC serial link.
1. I = input, O = output, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 8. Pin Descriptions--Transmit Add Equipment Interface (continued) Pin J2 J3 C6 H2 H3 D6 G4 G5 E6 F2 F3 B5 F4 F5 C5 E2 E3 D5 D9 Symbol ADATA_11 ADATA_11N TADCC_11 ADATA_12 ADATA_12N TADCC_12 ADATA_13 ADATA_13N TADCC_13 ADATA_14 ADATA_14N TADCC_14 ADATA_15 ADATA_15N TADCC_15 ADATA_16 ADATA_16N TADCC_16 TADCK Type1 I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O I LVDS O O Name/Description Transmit add STS-12 channel 11 serial data (622 MHz). Transmit add STS-12 channel 11 section DCC serial link. Transmit add STS-12 channel 12 serial data (622 MHz). Transmit add STS-12 channel 12 section DCC serial link. Transmit add STS-12 channel 13 serial data (622 MHz). Transmit add STS-12 channel 13 section DCC serial link. Transmit add STS-12 channel 14 serial data (622 MHz). Transmit add STS-12 channel 14 section DCC serial link. Transmit add STS-12 channel 15 serial data (622 MHz). Transmit add STS-12 channel 15 section DCC serial link. Transmit add STS-12 channel 16 serial data (622 MHz). Transmit add STS-12 channel 16 section DCC serial link. Transmit add STS-12 section DCC clock--all channels.
1. I = input, O = output, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 9. Pin Descriptions--LVDS Reference, Equipment Interface Pin M1 Symbol CTAP_ADD1 Type1 I LVDS Term I LVDS Term I LVDS Term I LVDS Term I I I I Name/Description Center Tap for ADATA_1 Through ADATA_4 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for ADATA_5 Through ADATA_8 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for ADATA_9 Through ADATA_12 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. Center Tap for ADATA_13 Through ADATA_16 Inputs. Provides center-tapped common-mode termination. This input should be terminated through an external 0.01 F capacitor to ground. 1.0 V 3% reference voltage for equipment interface I/Os. An example circuit is shown in Figure 3. 1.4 V 3% reference voltage for equipment interface I/Os. An example circuit is shown in Figure 3. Connect a 100 1% resistor between these pins.
L4
CTAP_ADD2
H5
CTAP_ADD3
E4
CTAP_ADD4
AK5 AL2 AL3 AL4
REF10E REF14E RESHIE RESLOE
1. I = input. I LVDS term = low-voltage differential signal termination pin.
3.3 V
3.3 V
2.32 k 1% LVDSREF10 LVDSREF14
1.91 k 1%
1 k 1%
1.43 k 1%
10 nF
10 nF
0622(F)
Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 10. Pin Descriptions--Transport Overhead Interface Pin AP28 AL27 AM25 AN26 AM27 AN27 AP26 AR26 AP27 AR27 AL26 AM26 E28 D28 B29 E29 C29 C30 Symbol REXPOW_1 RLCLOW_1 RSUSER_1 ROW_CLK_1 RLDCC_1 RLD_CLK_1 RSDCC_1 RSD_CLK_1 ROHDAT_1_0 ROHDAT_1_1 ROHFP_1 ROH_CLK_1 TEXPOW_1 TLCLOW_1 TSUSER_1 TOW_CLK_1 TLDCC_1 TLD_CLK_1 Type1 O O O O O O O O O O O O I I I O I O Name/Description STS_MODE = 1: STS-48 receive channel 1 express orderwire. STS_MODE = 0: STS-192 receive channel 1 express orderwire. STS_MODE = 1: STS-48 receive channel 1 local orderwire. STS_MODE = 0: STS-192 receive channel 1 local orderwire. STS_MODE = 1: STS-48 receive channel 1 section user channel. STS_MODE = 0: STS-192 receive channel 1 section user channel. STS_MODE = 1: STS-48 receive channel 1 orderwire/user clock. STS_MODE = 0: STS-192 receive channel 1 orderwire/user clock. STS_MODE = 1: STS-48 receive channel 1 line DCC. STS_MODE = 0: STS-192 receive channel 1 line DCC. STS_MODE = 1: STS-48 receive channel 1 line DCC clock. STS_MODE = 0: STS-192 receive channel 1 line DCC clock. STS_MODE = 1: STS-48 receive channel 1 section DCC. STS_MODE = 0: STS-192 receive channel 1 section DCC. STS_MODE = 1: STS-48 receive channel 1 section DCC clock. STS_MODE = 0: STS-192 receive channel 1 section DCC clock. STS_MODE = 1: STS-48 receive channel 1 TOH data (LSB). STS_MODE = 0: Receive STS-1 channel 1--48 TOH data (LSB). STS_MODE = 1: STS-48 receive channel 1 TOH data (MSB). STS_MODE = 0: Receive STS-1 channel 1--48 TOH data (MSB). STS_MODE = 1: STS-48 receive channel 1 TOH frame pulse. STS_MODE = 0: Receive STS-1 channel 1--48 TOH frame pulse. STS_MODE = 1: STS-48 receive channel 1 TOH clock. STS_MODE = 0: Receive STS-1 channel 1--48 TOH clock. STS_MODE = 1: STS-48 transmit channel 1 express orderwire. STS_MODE = 0: STS-192 transmit channel 1 express orderwire. STS_MODE = 1: STS-48 transmit channel 1 local orderwire. STS_MODE = 0: STS-192 transmit channel 1 local orderwire. STS_MODE = 1: STS-48 transmit channel 1 section user channel. STS_MODE = 0: STS-192 transmit channel 1 section user channel. STS_MODE = 1: STS-48 transmit channel 1 orderwire/user clock. STS_MODE = 0: STS-192 transmit channel 1 orderwire/user clock. STS_MODE = 1: STS-48 transmit channel 1 line DCC. STS_MODE = 0: STS-192 transmit channel 1 line DCC. STS_MODE = 1: STS-48 transmit channel 1 line DCC clock. STS_MODE = 0: STS-192 transmit channel 1 line DCC clock.
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 10. Pin Descriptions--Transport Overhead Interface (continued) Pin D29 B30 E30 B31 C31 D31 D30 AN25 AP25 AP23 AL23 AR25 AL24 AM23 AN23 AM24 AN24 AP24 AR24 Symbol TSDCC_1 TSD_CLK_1 TOHDAT_1_0 TOHDAT_1_1 TOHEN_1 TOHFP_1 TOH_CLK_1 REXPOW_2 RLCLOW_2 RSUSER_2 ROW_CLK_2 RLDCC_2 RLD_CLK_2 RSDCC_2 RSD_CLK_2 ROHDAT_2_0 ROHDAT_2_1 ROHFP_2 ROH_CLK_2 Type1 I O I I I O O O O O O O O O O O O O O Name/Description STS_MODE = 1: STS-48 transmit channel 1 section DCC. STS_MODE = 0: STS-192 transmit channel 1 section DCC. STS_MODE = 1: STS-48 transmit channel 1 section DCC clock. STS_MODE = 0: STS-192 transmit channel 1 section DCC clock. STS_MODE = 1: STS-48 transmit channel 1 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channel 1--48 TOH data (LSB). STS_MODE = 1: STS-48 transmit channel 1 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channel 1--48 TOH data (MSB). STS_MODE = 1: STS-48 transmit channel 1 TOH insert enable. STS_MODE = 0: Transmit STS-1 channel 1--48 TOH insert enable. STS_MODE = 1: STS-48 transmit channel 1 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channel 1--48 TOH frame pulse. STS_MODE = 1: STS-48 transmit channel 1 TOH clock. STS_MODE = 0: Transmit STS-1 channel 1--48 TOH clock. STS_MODE = 1: STS-48 receive channel 2 express orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 local orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 section user channel. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 orderwire/user clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 line DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 line DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 section DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 section DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 2 TOH data (LSB). STS_MODE = 0: Receive STS-1 channel 49--96 TOH data (LSB). STS_MODE = 1: STS-48 receive channel 2 TOH data (MSB). STS_MODE = 0: Receive STS-1 channel 49--96 TOH data (MSB). STS_MODE = 1: STS-48 receive channel 2 TOH frame pulse. STS_MODE = 0: Receive STS-1 channel 49--96 TOH frame pulse. STS_MODE = 1: STS-48 receive channel 2 TOH clock. STS_MODE = 0: Receive STS-1 channel 49--96 TOH clock.
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 10. Pin Descriptions--Transport Overhead Interface (continued) Pin B26 B25 C26 C25 E26 D25 A27 A26 B27 C27 D27 C28 B28 AL22 AM22 AN20 AP21 AN22 AP22 Symbol TEXPOW_2 TLCLOW_2 TSUSER_2 TOW_CLK_2 TLDCC_2 TLD_CLK_2 TSDCC_2 TSD_CLK_2 TOHDAT_2_0 TOHDAT_2_1 TOHEN_2 TOHFP_2 TOH_CLK_2 REXPOW_3 RLCLOW_3 RSUSER_3 ROW_CLK_3 RLDCC_3 RLD_CLK_3 Type1 I I I O I O I O I I I O O O O O O O O Name/Description STS_MODE = 1: STS-48 transmit channel 2 express orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 local orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 section user channel. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 orderwire/user clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 line DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 line DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 section DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 section DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 2 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channel 49--96 TOH data (LSB). STS_MODE = 1: STS-48 transmit channel 2 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channel 49--96 TOH data (MSB). STS_MODE = 1: STS-48 transmit channel 2 TOH insert enable. STS_MODE = 0: Transmit STS-1 channel 49--96 TOH insert enable. STS_MODE = 1: STS-48 transmit channel 2 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channel 49--96 TOH frame pulse. STS_MODE = 1: STS-48 transmit channel 2 TOH clock. STS_MODE = 0: Transmit STS-1 channel 49--96 TOH clock. STS_MODE = 1: STS-48 receive channel 3 express orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 local orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 section user channel. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 orderwire/user clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 line DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 line DCC clock. STS_MODE = 0: Not used.
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 10. Pin Descriptions--Transport Overhead Interface (continued) Pin AR21 AM20 AR22 AL21 AM21 AN21 E22 C22 D22 B23 E23 C23 A24 D23 B24 C24 D24 A25 Symbol RSDCC_3 RSD_CLK_3 ROHDAT_3_0 ROHDAT_3_1 ROHFP_3 ROH_CLK_3 TEXPOW_3 TLCLOW_3 TSUSER_3 TOW_CLK_3 TLDCC_3 TLD_CLK_3 TSDCC_3 TSD_CLK_3 TOHDAT_3_0 TOHDAT_3_1 TOHEN_3 TOHFP_3 Type1 O O O O O O I I I O I O I O I I I O Name/Description STS_MODE = 1: STS-48 receive channel 3 section DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 section DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 3 TOH data (LSB). STS_MODE = 0: Receive STS-1 channels 97--144 TOH data (LSB). STS_MODE = 1: STS-48 receive channel 3 TOH data (MSB). STS_MODE = 0: Receive STS-1 channels 97--144 TOH data (MSB). STS_MODE = 1: STS-48 receive channel 3 TOH frame pulse. STS_MODE = 0: Receive STS-1 channels 97--144 TOH frame pulse. STS_MODE = 1: STS-48 receive channel 3 TOH clock. STS_MODE = 0: Receive STS-1 channels 97--144 TOH clock. STS_MODE = 1: STS-48 transmit channel 3 express orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 local orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 section user channel. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 orderwire/user clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 line DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 line DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 section DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 section DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 3 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channels 97--144 TOH data (LSB). STS_MODE = 1: STS-48 transmit channel 3 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channels 97--144 TOH data (MSB). STS_MODE = 1: STS-48 transmit channel 3 TOH insert enable. STS_MODE = 0: Transmit STS-1 channels 97--144 TOH insert enable. STS_MODE = 1: STS-48 transmit channel 3 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channels 97--144 TOH frame pulse.
1. I = input, O = output. All I/O not explicitly stated with a buffer type 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 10. Pin Descriptions--Transport Overhead Interface (continued) Pin E24 AP20 AL19 AL17 AP18 AM19 AN19 AR17 AN17 AP19 AN18 AL18 AM18 D19 E19 B19 D20 B20 A21 Symbol TOH_CLK_3 REXPOW_4 RLCLOW_4 RSUSER_4 ROW_CLK_4 RLDCC_4 RLD_CLK_4 RSDCC_4 RSD_CLK_4 ROHDAT_4_0 ROHDAT_4_1 ROHFP_4 ROH_CLK_4 TEXPOW_4 TLCLOW_4 TSUSER_4 TOW_CLK_4 TLDCC_4 TLD_CLK_4 Type1 O O O O O O O O O O O O O I I I O I O Name/Description STS_MODE = 1: STS-48 transmit channel 3 TOH clock. STS_MODE = 0: Transmit STS-1 channels 97--144 TOH clock. STS_MODE = 1: STS-48 receive channel 4 express orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 local orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 section user channel. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 orderwire/user clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 line DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 line DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 section DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 section DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 receive channel 4 TOH data (LSB). STS_MODE = 0: Receive STS-1 channels 145--192 TOH data (LSB). STS_MODE = 1: STS-48 receive channel 4 TOH data (MSB). STS_MODE = 0: Receive STS-1 channels 145--192 TOH data (MSB). STS_MODE = 1: STS-48 receive channel 4 TOH frame pulse. STS_MODE = 0: Receive STS-1 channels 145--192 TOH frame pulse. STS_MODE = 1: STS-48 receive channel 4 TOH clock. STS_MODE = 0: Receive STS-1 channels 145--192 TOH clock. STS_MODE = 1: STS-48 transmit channel 4 express orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 local orderwire. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 section user channel. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 orderwire/user clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 line DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 line DCC clock. STS_MODE = 0: Not used.
1. I = input, O = output. All I/O not explicitly stated with a buffer type 3.3 V TTL.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 10. Pin Descriptions--Transport Overhead Interface (continued) Pin C20 B21 C21 E21 D21 B22 A22 Symbol TSDCC_4 TSD_CLK_4 TOHDAT_4_0 TOHDAT_4_1 TOHEN_4 TOHFP_4 TOH_CLK_4 Type1 I O I I I O O Name/Description STS_MODE = 1: STS-48 transmit channel 4 section DCC. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 section DCC clock. STS_MODE = 0: Not used. STS_MODE = 1: STS-48 transmit channel 4 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channels 145--192 TOH data (LSB). STS_MODE = 1: STS-48 transmit channel 4 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channels 145--192 TOH data (MSB). STS_MODE = 1: STS-48 transmit channel 4 TOH insert enable. STS_MODE = 0: Transmit STS-1 channels 145--192 TOH insert enable. STS_MODE = 1: STS-48 transmit channel 4 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channels 145--192 TOH frame pulse. STS_MODE = 1: STS-48 transmit channel 4 TOH clock. STS_MODE = 0: Transmit STS-1 channels 145--192 TOH clock.
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 11. Pin Descriptions--Microprocessor Interface Pin C14 Symbol PCLK Type1 I Name/Description Microprocessor Clock. This clock can operate at up to 78 MHz when the microprocessor interface is in asynchronous mode (MPMODE = 0). This clock can operate to a maximum of 40 MHz when the microprocessor interface is in synchronous mode (MPMODE = 1). Chip Select (Active-Low). This signal must be low during register access. Transfer Start or Address Strobe (Active-Low). Transfer start (TS_N) when MPMODE = 1 (synchronous). Address strobe (AS_N) when MPMODE = 0 (asynchronous). Data Strobe (Active-Low). This signal, when used in the asynchronous mode (MPMODE = 0), indicates that the data is valid for MPU writes. Read/Write. This signal is used to indicate a read or write operation. 1 = Read. 0 = Write. Data Transfer Acknowledge (Active-Low). This signal goes low to acknowledge the completion of a data transfer cycle. Transfer Error Acknowledge (Active-Low). This signal goes low to indicate an internal error related to the data transfer cycle. This is used only when the microprocessor interface is in synchronous mode (MPMODE = 1). Interrupt (Active-Low). This signal goes low when the device generates an unmasked interrupt. The interrupt signal is cleared when the unmasked raw alarm that generated the interrupt is cleared. Address Bus [15:0]. This bus is used to address registers. ADDRESS_15 is the MSB, ADDRESS_0 is the LSB.
A14 E15
CS_N TS_N (AS_N) DS_N RW_N
I I
D15 B14
I I
B13 C13
TA_N TEA_N
O O
D13
INT_N
O
C19 A19 B18 D18 E18 C18 B17 C17 D17 E17 B16 C16 D16 A15 B15 C15
ADDRESS_15 ADDRESS_14 ADDRESS_13 ADDRESS_12 ADDRESS_11 ADDRESS_10 ADDRESS_9 ADDRESS_8 ADDRESS_7 ADDRESS_6 ADDRESS_5 ADDRESS_4 ADDRESS_3 ADDRESS_2 ADDRESS_1 ADDRESS_0
I I I I I I I I I I I I I I I I
1. I/O = bidirectional pin, I = input, O = output. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 11. Pin Descriptions--Microprocessor Interface (continued) Pin A9 E10 D10 C10 B10 A10 D11 C11 B11 A11 E12 D12 C12 B12 A12 E13 C9 Symbol DATA_15 DATA_14 DATA_13 DATA_12 DATA_11 DATA_10 DATA_9 DATA_8 DATA_7 DATA_6 DATA_5 DATA_4 DATA_3 DATA_2 DATA_1 DATA_0 PARITY_0 Type1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Data Bus Parity--Lower Byte. Odd parity for lower byte [7:0], when MPMODE = 1 (synchronous). Unused when MPMODE = 0 (asynchronous); may be left unconnected if not used. Data Bus Parity--Upper Byte. Odd parity for upper byte [15:8], when MPMODE = 1 (synchronous). Unused when MPMODE = 0 (asynchronous); may be left unconnected if not used. Name/Description Data Bus [15:0]. This bus is a bidirectional data bus for writing and reading software registers. DATA_15 is the MSB, DATA_0 is the LSB.
B9
PARITY_1
I/O
1. I/O = bidirectional pin, I = input, O = output. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs.
Table 12. Pin Descriptions--JTAG Interface Pin AM29 AN30 AL29 AM30
1 Symbol Type
Name/Description Test Clock. This signal provides timing for test operations. Test Mode Select. Controls test operations. TMS is sampled on the rising edge of TCK. Test Data In. TDI is sampled on the rising edge of TCK. Test Data Out. This output is updated on the falling edge of TCK. The TDO output is 3-stated except when scanning out test data. Test Reset (Active-Low). This signal provides an asynchronous reset for the TAP. This input should be tied low (to VSS) for normal device operation. If TRST_N is high, a TCK must be present to ensure that the correct test mode is clocked in on the TMS input.
TCK TMS TDI TDO
Id Id Id O Iu
AP30 TRST_N
1. O = output, Id = input with internal pull-down resistor, Iu = input with internal pull-up resistor. The value of all internal pull-up/pull-down resistors is 50 k. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 13. Pin Descriptions--PLL References Pin G2 V3 AA5 AD5 AJ3 Symbol REXT_ADD REXT_DRP1 REXT_DRP2 REXT_DRP3 REXT_DRP4 Type1 I I I I I Name/Description External PLL Bypass Resistor for Add Interface. Should be externally connected through a 100 k resistor to analog ground (VSSA). External PLL Bypass Resistor for Drop Interface STS-48 #1. Should be externally connected through a 100 k resistor to analog ground (VSSA). External PLL Bypass Resistor for Drop Interface STS-48 #2. Should be externally connected through a 100 k resistor to analog ground (VSSA). External PLL Bypass Resistor for Drop Interface STS-48 #3. Should be externally connected through a 100 k resistor to analog ground (VSSA). External PLL Bypass Resistor for Drop Interface STS-48 #4. Should be externally connected through a 100 k resistor to analog ground (VSSA).
1. I = input. All inputs in Table 13 are 3.3 V TTL.
Table 14. Pin Descriptions--Power and Ground Pin A1, A2, A17, A18, A34, A35, B1, B2, B34, B35, C3, C33, E11, E25, L5, L31, U35, V1, V35, W1, AE5, AE31, AL11, AL25, AN3, AN33, AP1, AP2, AP34, AP35, AR1, AR2, AR18, AR19, AR34, AR35 A5, A6, A30, A31, D4, D32, E1, E5, E16, E20, E31, E35, F1, F35, T5, T31, Y5, Y31, AK1, AK35, AL1, AL5, AL16, AL20, AL31, AL35, AM4, AM32, AR5, AR6, AR30, AR31
1. P = power, G = ground.
Symbol VDD
Type1 P
Name/Description 3.3 V Positive Supply Voltage.
VDD2
P
2.5 V Positive Supply Voltage.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Pin Information (continued)
Table 14. Pin Descriptions--Power and Ground (continued) Pin A3, A4, A7, A8, A13, A16, A20, A23, A28, A29, A32, A33, B3, B4, B32, B33, C1, C2, C4, C32, C34, C35, D1, D2, D3, D33, D34, D35, G1, G35, H1, H35, N1, N35, T1, T35, Y1, Y35, AC1, AC35, AH1, AH35, AJ1, AJ35, AM1, AM2, AM3, AM33, AM34, AM35, AN1, AN2, AN4, AN32, AN34, AN35, AP3, AP4, AP32, AP33, AR3, AR4, AR7, AR8, AR13, AR16, AR20, AR23, AR28, AR29, AR32, AR33 J4, T2, Y4, AD2, AH3 Symbol VSS Type1 G Digital Ground. Name/Description
VDDA
P
Analog Positive Supply Voltage for PLL Circuits. 3.3 Vdc supply for PLL circuitry. Each should be connected in such a way that EMI is decoupled between VDDAs, and to or from VDD. The maximum analog PLL power is 350 mW for the device.
s s
J4 is the power supply for the add interface PLL. T2, Y4, AD2, and AH3 are the power supplies for the drop interface PLLs.
J5, T3, Y3, AD1, AH2
VSSA
G
Analog Ground for PLL Circuits. Ground for the PLL circuitry. These should be connected to VSS in a manner appropriate to minimize EMI between VSSA pins, and between VSS and VSSA.
s s
J5 is the analog ground for the add interface PLL. T3, Y3, AD1, and AH2 are the analog grounds for the drop interface PLLs.
1. P = power, G = ground.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Pin Information (continued)
Table 14. Pin Descriptions--Power and Ground (continued) Pin AP6, AL7, AN16, AM16 AM5, AN5, AP5, AL6, AM6, AN6, AM7, AN7, AP7, AL10, AM10, AN10, AP10, AR10, AN28, AM28, AL28, AP29 AL8, AL9, AM8, AM9, AN8, AN9, AP8, AP9, AN29, AR9, D262, E272, G32, H42, J12, K32, K312, L32, M332, N22, N52, P42, R32, T42, T322, U22, U32, U312, Y22, AB12, AC22, AC52, AF12, AG12, AH342, AJ22, AK42 Symbol PULLUP PULLDN Type1 -- -- Name/Description Manufacturing Test. These pins must be individually pulled up to VDD2 through 47 k resistors for normal operation. Manufacturing Test. These pins must be individually pulled down to VSS through 47 k resistors for normal operation.
NC
--
No Connect. Do not connect to these pins.
1. P = power, G = ground. 2. No connect (NC) pins indicated with a footnote (2) are unused. There is no connection between the pin and the die.
Table 15. Pin Summary Pin Type LVDS Pin Direction Input Output Reference Input Output Bidirectional Count 76 96 27 81 93 20 37 20 73 77 600
TTL
NC Other (Manufacturing Test) Power Ground Total
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description
Receive STS-192 Line Interface
The receive STS-192 line interface is configured to accept either a single 16-bit wide serial STS-192 stream at 622.08 MHz or four 4-bit wide serial STS-48 streams at 622.08 MHz, and convert them to four STS-48 streams. The conversion process is essentially the same for both input formats, except that for STS-48 data, each function is divided into four independent blocks running on separate clocks, while the STS-192 data is processed in one block and must be passed through a time-slot interchange (TSI) block after the conversion process to demultiplex its four constituent STS-48 channels. Regardless of which line format is being used, each input serial stream is first byte and frame aligned by passing it through a bit rotator to align it. The frame alignment used by the bit rotator is determined by a framer circuit which monitors the nonaligned word. The data from the bit rotator is then passed to a BIP-8 parity calculator before being optionally descrambled. The descrambled data is then either passed directly to one of the STS-48 processing modules when in STS-48 mode, or first passed to a TSI when in STS-192 mode. This TSI reorders the STS-1 slots within the STS-192 to appear as four STS-48 signals, as required by the STS-48 processing modules. In STS-192 mode, all 16 data streams are clocked on the positive edge of R_CLK_1. In STS-48 mode, the four data streams associated with each STS-48 are clocked in on the positive edge of a corresponding clock, R_CLK_n. Loss-of-Signal (LOS) Detector Before the data is optionally descrambled, it is monitored for loss-of-signal (LOS). In STS-192 mode, there is a single LOS detector. In STS-48 mode, there is a separate LOS detector on each STS-48 input. On powerup, an LOS defect is declared if all zeros data is received continuously for 13.8 s. This time threshold is provisionable through the loss-of-signal (LOS) threshold register for each channel, and can be set to any value from 0 s (i.e., LOS detection disabled) to 105 s, with a resolution of 102.88 ns (64 times the period of the 622.08 MHz clock). The LOS defect is subsequently cleared when two successive valid framing patterns are received with no period of all zeros exceeding the time threshold. Detection of an LOS defect is indicated by a latched alarm status bit, a persistency bit, and a one second PM bit being set in the corresponding LTE receive channel n registers. In addition, alarm indication signal (AIS) will be inserted by the framer block in all 48 or 192 STS-1 channels affected. If an optical transponder is connected to the receive line interface, the most appropriate method to declare LOS is by monitoring the power level monitor of the received signal from the transponder. In some transponders, the amplifier gain is high enough to cause the LVDS receive data lines to move above zero, even when there is no optical input. Should this occur, the TSOT0410G4 might not indicate an LOS defect. This is not a deficiency of the devices, but is a characteristic of the methods of detecting LOS. If an optical transponder is used, the LOS detector of the TSOT0410G4 monitors the connection from the transponder to the receive line interface. The LOS detector in the TSOT0410G4 is appropriate for monitoring LOS in an electrical SONET or SDH system.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Note: Register summary tables occur throughout the Functional Description section on page 47, and describe the first occurrence of registers that are used for a particular function. Refer to the register map (Table 71 on page 97) for details on other occurrences of similar registers. Table 16. LOS Detector Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Loss-of-Signal (LOS) Threshold (R/W) LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO) LTE Receive Channel 1 Performance Monitoring (RO) Register Bits Qty.1 1st Page3 Addr2 (hex) 1402 1405 123 124
LOS Detect Time Latched LOS Alarm
LTE_RX_n_LOS_ THRESHOLD1[9:0] LOS
4 4
LOS Persistency
LOS_PER
4
1407
124
LOS One Second PM
LOS_PM
4
140B
127
1. Qty. refers to the number of registers that are similar to the one shown in the table. There may be more registers to control different channels, or several registers of similar type used for a particular function. 2. 1st Addr refers to the address (in hex) of the first occurrence of this type of register. 3. Page refers to the relevant page number in this document.
Framer (A1 and A2) In STS-192 mode, when in frame, the framer outputs byte-aligned and frame-aligned data. In STS-48 mode, framing is performed on four independent channels. Frame timing, parity generation, and AIS insertion are also performed. Enhanced framing, where every other A1 and A2 byte is inverted to better maintain the dc balance on the optical line, is also supported in STS-192 mode. A1A1A1A1 . . . A1A1 = F609F609 . . . F609. A2A2A2A2 . . . A2A2 = 28D728D7 . . . 28D7. The STS-192 framer is described below. The STS-48 framer is similar. Enhanced framing is not used when in STS-48 mode (it is not part of the SONET/SDH specifications). Bit 1 of registers 0x1C00, 0x1D00, 0x1E00, and 0x1F00 should be set to normal mode when the TSOT0410G4 is operating in STS-48 mode. Framer FSM. The framer FSM is responsible for determining the severely errored framing (SEF) and loss-of-framing (LOF) SONET framing alarms for each channel. The framer FSM is shown in Figure 4 on page 49. The FSM comes out of reset in the SEF state with the SEF and LOF alarms active. The framing pattern used is the 16-bit word consisting of the last A1 byte, the first A2 byte, plus two additional A1 bytes. The first occurrence of the framing pattern transfers the FSM to the frame confirm state. Frame timing is also synchronized. Another framing pattern match coincident with expected frame timing transfers the state to in frame (i.e., it takes two consecutive valid framing patterns to frame to an incoming signal). Outside the SEF and frame confirm states, the SEF alarm output is inactive. As shown in the FSM, when in frame, it requires four consecutive framing errors to be transferred back to the SEF state.
s s
The LOF alarm is asserted if SEF persists for 24 frames (3 ms). The LOF alarm is terminated eight frames (1 ms) after the SEF alarm is terminated (i.e., eight frames after the FSM enters the in-frame state), provided the SEF state is not re-entered (as per SONET objectives). Agere Systems Inc.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
IN FRAME
FRAMING PATTERN CONFIRMED
FRAME CONFIRM
FOUR CONSECUTIVE FRAMING ERRORS
FRAMING PATTERN NOT COMFIRMED FRAMING PATTERN FOUND
SEF
RESET
5-8401(F).a
Figure 4. Framer FSM The framing pattern is a subset of the A1A2 STS-N pattern. This design uses the 16-bit A1A2 boundary as the framing pattern which evaluates to an average SEF defect occurrence time of 31.79 minutes, assuming a Poisson bit error rate (BER) of 10-3. This is greater than the minimum average SONET requirement of 6 minutes. The SEF alarm is reported by a latched register bit in the LTE receive nonservice-affecting alarm register for the respective channel. The LOF alarm is reported by a latched register bit in the LTE receive service-affecting alarm register for the respective channel. In addition, a persistency bit for LOF exists in the LTE receive service-affecting persistency register. Detection of LOF and SEF defects are also indicated by the LTE receive last second PM register. On powerup, detection of an LOF defect causes AIS to be inserted in all affected STS-1 channels by the framer. During AIS insertion, transport overhead (TOH) processing is disabled. This AIS insertion can be disabled using the LOF AIS disable control register bit for each channel, or replaced by insertion upon SEF detection using the SEF AIS disable control bit. Another control bit is the enhanced framing mode. These control bits are part of the LTE receive provisioning register for the respective channel. The framer is also responsible for sourcing parity with the framed channels. Parity errors can be forced using the chip-level maintenance register.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 17. Framer Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Provisioning (R/W) LTE Receive Channel 1 Provisioning (R/W) LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO) LTE Receive Channel 1 Performance Monitoring (RO) Chip-Level Maintenance (R/W) Register Bits Qty. 1st Addr (hex) 1400 1400 1405 Page
Enhanced Framing AIS Insertion on SEF, LOF LOF Latched Alarm
ENH_FRMG_CTL_1 SEF_AIS_DIS_1 LOF_AIS_DIS_1 LOF
4 4 4
122 122 124
SEF Latched Alarm
SEF
4
1408
125
LOF Persistency
LOF_PER
4
1407
124
LOF, SEF One Second PM Forcing Parity Errors Descrambler
LOF_PM SEF_PM FRC_PAR_ERR
4 1
140B 0005
127 112
The data from the framer is descrambled using the SONET/SDH standard generator polynomial: 1 + x6 + x7. The descrambling can be disabled through the DESCRM_DIS bit in the LTE receive channel provisioning register for each channel. Table 18. Descrambler Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Provisioning (R/W) Register Bits Qty. 1st Addr (hex) 1400 Page
Descrambling Control
DESCRM_DIS_1
4
122
Time-Slot Interchanger (TSI) For STS-192 data, the input stream must be demultiplexed to create four STS-48 data streams for further processing. The TSI reorders the data so that the STS-192 is divided into its four constituent STS-48 data streams. Table 19 on page 51 shows the order of the bytes belonging to the individual STS-1s, or STS-1, components of an STS-Nc that comprise the STS-192 as it enters the TSI. Table 20 on page 51 shows the order of bytes after the TSI (STS-48 byte ordering). In the tables, the bytes arrive starting in the top left of the table, and then down each column. The STS-48 table should be interpreted as four simultaneous data streams, where the bytes are ordered starting with the top left of each channel, and then down each column. If the TSOT0410G4 is in STS-48 mode, the data is received on all four channels and the TSI is bypassed.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Table 19. STS-192 Byte Ordering Time (Top to Bottom, Then Left to Right) 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97 100 103 106 109 112 115 118 121 124 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 172 175 178 181 184 187 190 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93 96 99 102 105 108 111 114 117 120 123 126 129 132 135 138 141 144 147 150 153 156 159 162 165 168 171 174 177 180 183 186 189 192 STS-192 Number 1
Table 20. STS-48 Byte Ordering Time (Top to Bottom, Then Left to Right for Each STS-48 Channel) 1 4 7 10 49 52 55 58 97 100 103 106 145 148 151 154 13 16 19 22 61 64 67 70 109 112 115 118 157 160 163 166 25 28 31 34 73 76 79 82 121 124 127 130 169 172 175 178 37 40 43 46 85 88 91 94 133 136 139 142 181 184 187 190 2 5 8 11 50 53 56 59 98 101 104 107 146 149 152 155 14 17 20 23 62 65 68 71 110 113 116 119 158 161 164 167 26 29 32 35 74 77 80 83 122 125 128 131 170 173 176 179 38 41 44 47 86 89 92 95 134 137 140 143 182 185 188 191 3 6 9 12 51 54 57 60 99 102 105 108 147 150 153 156 15 18 21 24 63 66 69 72 111 114 117 120 159 162 165 168 27 30 33 36 75 78 81 84 123 126 129 132 171 174 177 180 39 42 45 48 87 90 93 96 135 138 141 144 183 186 189 192 STS-48 Number 1
2
3
4
Note: STS-12 byte ordering is shown in Table 29 on page 62.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Receive Transport Overhead (TOH) Processor
This block is responsible for terminating the transport overhead and is replicated four times. Each block accepts the frame and byte-aligned data for one STS-48 channel and extracts the transport section and line overhead. The extracted overhead is then either stored internally, or provided externally on a serial output, and may also be further processed for alarm or performance monitoring purposes. In STS-48 mode, each channel is synchronized to a separate clock and carries complete transport overhead. In STS-192 mode, all channels are synchronized to the same clock and only the first STS-48 carries complete transport overhead, while the other channels only carry line BIP-8. The definition and associated storage or processing of each byte is detailed in the subsections that follow. All processing of overhead bytes is inhibited while the following alarm defects are detected:
s s s s
LOS (if not disabled) LOF (if AIS insertion is enabled) SEF (if AIS insertion is enabled) Line AIS (only the line overhead bytes are inhibited)
Receive Overhead Serial Links In addition to the individual storage or external availability of the overhead bytes described below, the full set of transport overhead bytes for each STS-48 channel (1296 bytes) are serialized and output on the ROHDAT_n_[1:0] pins. The bytes are sent, MSB first, with each pair of bits output on the positive edge of ROH_CLK_n (41.472 MHz). The location of the MSB of the first A1 byte is identified by the ROHFP_n output going high. In STS-48 mode, each pair of ROHDAT_n_[1:0] pins transmits the transport overhead for an STS-48 channel. In STS-192 mode, the four pairs of ROHDAT_n_[1:0] pins transmit the entire STS-192 overhead (5184 bytes), where the ROHDAT1 pins transmit STS channels 1 through 48, and the ROHDAT2, ROHDAT3, and ROHDAT4 pins transmit STS channels 49 through 96, 97 through 144, and 145 through 192, respectively. The timing for this is described in the Receive Overhead Serial Link section on page 175. Each interface determines its ROHFP by sampling the Rx frame using a metastable hand-off. Even in 10 Gbits/s mode, where the RXCLK and ROHCLK are the same, the different delays on the signals in each channel will create the potential for the metastable handlers to sample the channels, 1 clock cycles, of each other. This is unavoidable due to the possibility of the four channels being asynchronous. Any external logic that interfaces to ROHDAT should synchronize to each of the four channels independently using the individual ROHFP signals. Internally, a memory is used for each channel to buffer the data and transfer it between the internal processing rate and the external data rate. This allows for the data to be transmitted in a nongapped manner. The operation of the memory is monitored using parity, and any errors are reported using the ROHDAT parity error alarm bit. This alarm bit is present in the corresponding LTE receive channel n nonservice affecting interrupt alarm register and is valid regardless of the mode (STS-48 or STS-192) in which the device is operating. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0xFF is constantly output for the overhead byte values. Table 21. Receive Overhead Serial Links Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) Register Bits Qty. 1st Addr (hex) 1408 Page
Parity Alarm
RX_OH_MEM_PAR_ ERR_1
4
125
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Section Trace (J0) The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. Specified by the J0 message type control bit, the TOH processor supports extraction of either SONET 64-byte (ASCII, terminated) or SDH 16-byte (E.164) section trace messages that are stored in internal memory. Processing of the received message then depends on the J0 message mode control bit. The content of the message is either monitored for a mismatch from a provisioned expected message or monitored for a sustained change (validation) in the received message. If the J0 message mode control bit is set to the provisioned mode, then the incoming message is compared against the software programmed expected message. The expected message is stored in internal memory for each STS-48 channel. A mismatch is declared if a consistent received message differs from the expected message for ten consecutive messages. The mismatch clears when four out of five received messages match the expected message (fixed windowing is used for clearing). This mismatch state is reflected in the J0 message mismatch alarm bit. When the J0 message mode control bit is set to the validated mode, the incoming message is monitored for a sustained change. A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message, is stored in internal memory, and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). The J0 new message alarm bit is set when a sustained change is detected. Selection of the message type, SONET or SDH format, and the content monitoring mode (provisioned or validated), are provisionable on a per STS-48 channel basis through a corresponding LTE receive channel n maintenance register. The associated alarms for the two modes are reported in the LTE receive channel n nonservice-affecting interrupt alarm register. The expected messages for all channels are provisioned through the microprocessor interface using the 64-byte J0 access message buffer. This message buffer is also used to read the contents of the expected, stable, or received messages for all channels. Accesses using the data buffer are paged according to direction (transmit and receive), STS-48 channel, and message type (expected/stable or received) through the use of the section trace access register. If the J0 message mode is set to the provisioned mode, the expected message is accessible. If the J0 message mode is set to the validated mode, then the stable message is accessible. Once the section trace access register is configured, the actual access is triggered by writing a 0x0001 value to the section trace access start register. The transfer from internal memory to/from the message buffer is performed on the next message boundary. Completion of the access is indicated by the access done flag being set in the section trace access status register. Note: To insert J0 into the transmit stream, 0x0020 must be written register 0x1C01 (the enable insertion of provisioned J0 message register). See Table 137 on page 131 for detailed register information. Internally, a memory is used to store the currently received section trace message as well as the stable or provisioned message. The operation of the memory is monitored using parity, and any errors are reported using the J0 parity error alarm bit.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 22. J0 Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Maintenance (R/W) LTE Receive Channel 1 Maintenance (R/W) Register Bits Qty. 1st Page Addr (hex) 1401 1401 123 123
Message Type Control Message Mode (Provisioned or Validated) Message Mismatch Latched Alarm
J_MSG_TYPE_1 J_MSG_MODE_1
4 4
LTE Receive Channel 1 J_MSG_MISMATCH_INT Nonservice-Affecting Interrupt Alarm _1 (W1C) J_NEW_MSG_INT_1 New Message Latched LTE Receive Channel 1 Alarm Nonservice-Affecting Interrupt Alarm (W1C) J0 Access Message Buffer J0 Access Message Buffers 1--32 LTE_J_ACCESS_ (R/W) BUF_n[15:0] Message Buffer Access Section Trace (J0) Access All bits Control Maintenance (R/W) Message Buffer Access J0 Access Message Start (WO) LTE_J_ACCESS_MSG_ Start START Message Buffer Access J0 Access Done (W1C) J_ACCESS_DONE_ Complete Flag FLAG Buffer Parity Error Latched LTE Receive Channel 1 J_MEM_PARITY_ Alarm Nonservice-Affecting Interrupt Alarm ERR_1S (W1C)
4
1408
125
4
1408
125
32 1 1 1 4
1110 1100 1102 1101 1408
118 117 118 118 125
Section Growth (Z0) No receive function has currently been defined for the section growth byte present in the remaining STS-1 locations of the STS-48 or STS-192 J0 byte. Section BIP-8 (B1) The section BIP-8 byte is located in the first STS-1 of the STS-48 or STS-192 only, and carries the even parity of the scrambled data in the previous STS-48 or STS-192 frame. In every frame, the received B1 value is extracted and compared to the calculated BIP-8 for the previous frame. Errors in the BIP-8 code are tabulated in an internal 16-bit counter based on either bit or block errors as provisioned for each channel through the B1 BIP mode control bit. In bit mode (selected by default), each BIP-8 bit in error causes the counter to increment. If block error is selected, each BIP-8 code in error causes the counter to increment only once. Regardless of which mode is selected, the value in the counter is transferred to the section coding violation (CV-S) register on the positive edge of PM_CLK, at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. Section BIP-8 (B1) Errors Serial Access The errors detected in section BIP-8 byte are located in the first STS-1 of the STS-48 or STS-192 and can optionally be extracted serially on the local the ROHDAT interface. See the Receive Overhead Serial Links section on page 52 for details on the ROHDAT interface. A provisioning bit (B1_ERROR_MASK_EN (bit 7)) is provided in each LTE Rx channel provisioning register as a B1 error mask enable. When the B1_ERROR_MASK_EN bit is set, the B1 byte in ROHDAT is replaced with the B1 error mask from the previous frame. An error in the Rx B1 BIP-8 code will result in the corresponding bit in the error mask being set for one frame, with a one-frame delay due to retiming. 54 Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
The ROHDAT interface B1 error mask extraction is enabled by provisioning the B1_ERROR_MASK_EN bit in the LTE Rx channel provisioning registers (0x1400, 0x1500, 0x1600, and 0x1700 respectively). (See Table 110 on page 122.) The appropriate bit definitions are shown in Table 23. The B1 error mask extract feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. Table 23. B1 Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Page Addr (hex) 1400 122 1400 122 1410 128
B1 Error Bit Enable Bit Error/Block Error Control Last Second Coding Violations Count Local Orderwire (E1)
LTE Receive Channel 1 Provisioning (R/W) B1_ERROR_MASK_EN LTE Receive Channel 1 Provisioning (R/W) B1_BIP_MODE_1 LTE Receive Channel 1 CV-S Performance Monitoring (RO) CV_S_REG_1
4 4 4
The local orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for voice communications between regenerators, hubs, and remote terminals. The byte is extracted from each frame, buffered, and then output serially, MSB first, on the RLCLOWn pin. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0x7F is constantly output. The data is clocked out on the positive edge of ROWCKn. The ROWCKn clock is divided down from the section data communications channel clock, RSDCKn (192 kHz/3), giving a frequency of 64 kHz and a duty cycle of 33%. In STS-48 mode, each of the four RLCLOW pins transmit the E1 byte for a channel. In STS-192 mode, only the RLCLOW1 pin transmits the E1 byte, while the other pins transmit a constant 0x7F serial stream. Section User Channel (F1) The section user channel byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for use by the network provider. The byte is extracted in each frame, buffered, and output serially, MSB first, on the RSUSERn pin. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0x7F is constantly output. The data is clocked out on the positive edge of ROWCKn. In STS-48 mode, each of the four RSUSERn pins transmit the F1 byte for a channel. In STS-192 mode, only the RSUSER1 pin transmits the F1 byte, while the other pins transmit a constant 0x7F serial stream. Section Data Communications Channel (D1, D2, and D3) The section data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only and are used as one 192 kHz message-based channel for operations, administration, and maintenance (OA&M) communication. The bytes are extracted from each frame, buffered, and output serially, MSB first, on the RSDCCn pin in the order that they are received. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0xFF is constantly output. The data is clocked out on the positive edge of RSDCKn. The RSDCKn clock is divided down from the line data communications channel clock, RLDCKn (576 kHz/3), giving a frequency of 192 kHz and a duty cycle of 33%. In STS-48 mode, each of the four RSDCC pins transmit the section data communication channel bytes for a channel. In STS-192 mode, only the RSDCC1 pin transmits these bytes, while the other pins are set high.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Line BIP-8 (B2) The line BIP-8 is located in each STS-1 of the STS-48 or STS-192 and carries the even parity for the line overhead and SPE data within the previous STS-1 frame. The n line BIP-8 bytes in an STS-N are intended to provide a single error monitoring facility for the entire STS-N signal. Thus, each TOH processor block is used to check the 48 line BIP-8 codes, whether in STS-48 or STS-192 mode. Each BIP-8 bit found to be in error causes an internal 22-bit counter to increment. The value in the counter is transferred to the line coding violation (CV-L) registers on the positive edge of PM_CLK, at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. When in STS-192 mode, a read of the STS-48 channel 1 CV-L register returns the 24-bit sum of the four constituent STS-48 channel CV-L counts. However, reading channels 2--4 returns the CV-L count for the corresponding STS-48. In addition to the CV-L counter, line BIP-8 errors are also tracked in 16-bit signal fail (SF) and signal degrade (SD) counters. These counters are used to detect SF and SD conditions for protection switching. The BER threshold for each defect is separately provisionable for each channel over a range of 1 x 10-N values, where N = 3 to 5 for SF and N = 5 to 9 for SD. The detection times and error limits used to detect and clear both defects are dependent on the provisioned BER threshold as shown in Table 24. The values shown in the table are the powerup defaults and are dependent on the STS mode selected (48 or 192). These values can be changed through the corresponding registers and are common to all channels. The clearing BER threshold for each defect is always 1/10th of the detection threshold. As can be seen in Table 24, the range of possible detect thresholds is 1 x 10-3 to 1 x 10-9, which results in clear thresholds of 1 x 10-4 to 1 x 10-10. For example, to detect SD at 1 x 10-5 BER in an STS-192, the detection time is 4 ms and the detect error limit is 358. The clearing would take place at 1 x 10-6 BER, with a clearing time of 6.5 ms and a clearing error limit of 77. Figure 5 on page 57 illustrates SD detection and clearing using the default values specified in Table 24. SD thresholds of 1 x 10-10 to 1 x 10-15 are supported through software. Table 24. BER Threshold Time and Error Limits for Line SD and SF Detection BER Threshold 1 x 10-3 1 x 10 1 x 10 1 x 10 1 x 10
-4
Detection Time STS-48 4 ms 4 ms 4 ms 31 ms 312.5 ms 2600 ms 21 s 170 s STS-192 4 ms 4 ms 4 ms 6.5 ms 65 ms 650 ms 5250 ms 41 s
Detect Error Limit STS-48 4818 862 81 62 62 51 40 -- STS-192 19453 3543 358 51 51 51 40 --
Clear Error Limit STS-48 -- 957 114 91 91 77 63 52 STS-192 -- 3734 423 77 77 77 63 51
1 x 10-5
-6 -7 -8
1 x 10-9 1 x 10-10
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
358 SD ACCUMULATED B2 ERRORS
SD DETECTED
77 SD 4 SD DETECTION WINDOW 6 8 SD CLEARING WINDOW 12.5 19 TIME (MS)
5-8406(F)r.1
CLEARED
Figure 5. Example of STS-192 SD Detection (10-5 BER) and Clearing (10-6 BER) In STS-192 mode, the thresholds are compared against the sum of the four STS-48 channel SF and SD counts. A detected SF or SD defect causes a corresponding maskable interrupt status bit to be set in the LTE receive channel n service-affecting alarm register. The SD/SF BER control bits in the LTE receive channel n maintenance register select the bit error rate for a particular channel. These control bits then select the detection time, the detect error limit, and the clear error limits for each channel from the LTE receive common SD/SF registers. The detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper bit for a time unit specifier. For the detection time register, the value contained in the lower 15 bits is either specified in 0.5 ms units (upper bit = 0) or in seconds (upper bit = 1). Note that the PM_CLK input to the device is used as the timing reference when the detection time is expressed in seconds. A fixed windowing scheme is used for SD/SF detection. The window size is determined by the value in the detection time register for the specified bit error rate. An SD or SF alarm is declared immediately when the accumulated error count exceeds the value specified in the detect error limit register. If this error limit is not reached by the end of the window, then the accumulated error count is reset to zero. When an SD or SF alarm is declared, the accumulated error count resets and clearing begins using the bit error rate threshold that is 1/10th of the specified value along with the corresponding detection time registers. Clearing of the SD or SF alarm only occurs at the end of the window when the accumulated error count is less than the value specified in the clear error limit register. During AIS insertion due to LOS, LOF, SEF, or line AIS, processing of the B2 byte is inhibited and the internal SF/SD counters are reset back to zero. Because it takes five frames of line AIS before the actual line AIS alarm is declared, it is likely that the signal degrade alarm will also be triggered. Once AIS insertion is removed, processing of the B2 byte is delayed for two frames before it is enabled.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 25. B2 Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 140E/ 140F 1300 Page
Last Second Coding Violations LTE Receive Channel 1 CV-L CV_L_REG_1_L/ Count Performance Monitoring (L) (RO) CV_L_REG_1_U SD/SF Detection Time Line Signal Degrade/Signal Fail Bit SD_SF_DETECT_ Error Rate Detection Time TIME_3 (1 x 10-3) (R/W) SD_SF_ERR_ SD/SF Detect Error Limit Line Signal Degrade/Signal Fail LIMIT_3 Detect Error Limit (1 x 10-3) (R/W) SD_SF_CLR_ERR_ SD/SF Clear Error Limit Line Signal Degrade/Signal Fail LIMIT_3 Clear Error Limit (1 x 10-4) (R/W) SD/SF Threshold Selection LTE Receive Channel 1 SD_BER_1/ Maintenance (R/W) SF_BER_1 SD/SF Latched Alarms LTE Receive Channel 1 SD_ALARM_1/ Service-Affecting Interrupt Alarm SF_ALARM_1 (W1C) Line BIP-8 (B2) Errors Serial Access
4 8
127 119
7 7 4 4
1310 1320 1401 1405
120 121 123 124
The errors detected in the line BIP-8 (B2) byte for each STS-1 can optionally be extracted serially on the local orderwire (RLCLOWn), express orderwire (REXPOWn), and orderwire clock (OW_CLKn) pins of each STS-48. This extraction is enabled on a global basis (i.e., all channels) by provisioning the LTE Transmit--B2 Corrupt Frame Count (R/W) register (on page 128) with a value greater than 806310. The appropriate bit definitions are shown in Table 130 on page 128, register 1B02. The TOH transparency feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. When enabled, the B2 errors detected in each STS-1 of an STS-48 are output serially on the REXPOWn pin as a byte containing a 1 in each bit position found in error. These error masks are clocked out on the positive edge of a 78 MHz clock that is provided on the OW_CLKn pin. Because this frequency is much higher than the bit rate of the B2 bytes, the 48 error masks on each REXPOWn pin are output in a burst fashion once per frame. The presence of this burst is indicated by a continuous logical high on the RLCLOWn pin. The data within the burst follows SONET STS-1 channel ordering, but with the 48 channels serialized in 4-byte chunks with the LSB (newest data) sent first. In other words, the STS-1 error masks for each STS-48 are sent LSB first in the following order: 10, 7, 4, 1; 22, 19, 16, 13; 34, 31, 28, 25; 46, 43, 40, 37; 11, 8, 5, 2; 23, 20, 17, 14; 35, 32, 29, 26; 47, 44, 41, 38; 12, 9, 6, 3; 24, 21, 18, 15; 36, 33, 30, 27; 48, 45, 42, 39. APS Channel (K1 and K2) The APS channels bytes are located in the first STS-1 of the STS-48 or STS-192 only and are used for automatic protection switching (APS) signaling to coordinate line level protection switching. In addition, the K2 byte is also used to carry line AIS (AIS-L) and line RDI (RDI-L) signals. A new value in either byte is only validated after it has been received N times consecutively, where N is provisionable to 3 or 5 using the K1K2 validate select control bit. When a K1 or K2 byte is validated, the value is stored in the K byte status register and the K1K2 new byte alarm bit is set. These two alarms are only generated when the value of the new validated K1 or K2 byte is different from the value of the last validated byte. Validation of the K1 and K2 bytes, and the generation of the alarms, are not affected by the line AIS status.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
The validated K1 and K2 bytes are further processed for the following defects:
s
Protection switching byte. This defect occurs when either an inconsistent APS byte or an invalid code is detected. An inconsistent APS byte occurs when no N consecutive K1 bytes of the last 12 successive frames are identical, starting with the last frame containing a previously consistent byte. An invalid code occurs when the incoming K1 byte contains an unused code or a code irrelevant for the specific switching operation in three consecutive frames. An invalid code also occurs when the incoming K1 byte contains an invalid channel number in three consecutive frames. As invalid code detection requires information not readily available to hardware; it must be detected by software polling of the validated K1 byte value. An inconsistent APS byte defect is detected by hardware and will cause a latched alarm status bit to be set in the corresponding LTE receive channel n nonservice affecting interrupt alarm register. It is cleared when a K1 byte is received and validated. An inconsistent APS byte defect is neither detected nor terminated during AIS-L defect. Processing of the inconsistent APS byte defect is also inhibited when the validated K1 byte has a value of 0xFF and bits 6--8 of the validated K2 byte have a value of 111. This additional feature prevents a change in the inconsistent APS defect state just before line AIS is declared. Channel mismatch. This defect occurs when the channel numbers in the transmitted K1 byte (bits 5--8) and the validated received K2 byte (bits 1--4) are not identical. Detection of a channel mismatch defect causes a latched alarm status bit to be set in the corresponding LTE receive channel n nonservice-affecting interrupt alarm register. A channel mismatch defect is neither detected nor terminated during an AIS-L defect. Processing of the channel mismatch defect is also inhibited when the validated K2 byte has a value of 1111x111 binary. This additional feature prevents a change in the channel mismatch defect state just before line AIS is declared. Line AIS (AIS-L). Declared when bits 6--8 of K2 contain 111 for five consecutive frames. Cleared when any other pattern is received for five consecutive frames. Detection of a line AIS defect is indicated by a latched alarm status bit, persistency bit, and one second PM bit being set in the registers for the affected channel. Line RDI (RDI-L). Declared when bits 6--8 of K2 contain 110 (binary) for five consecutive frames. Cleared when any other pattern is received for five consecutive frames. Detection of a line RDI defect is indicated by a latched alarm status bit, persistency bit, and one second PM bit being set in the registers for the affected channel.
s
In addition, the currently received K2 byte is processed for the following defects:
s
s
Table 26. APS Channel (K1 and K2) Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Provisioning (R/W) LTE Receive Channel 1 K Byte Status (RO) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO) Register Bits Qty. 1st Addr (hex) 1400 1403 1408 Page
K1K2 Validation Length (3 or 5) Validated K1K2 Storage New Validated K1K2 Alarm Inconsistent APS Alarm Channel Mismatch Alarm AIS-L Latched Alarm AIS-L Persistency
K_VALIDATE_LIMIT_SEL_1 RX_K1_VALIDATED_BYTE_1 RX_K2_VALIDATED_BYTE_1 RX_K1_NEW_BYTE_RAW_INT_1 RX_K2_NEW_BYTE_RAW_INT_1 INCONSISTENT_APS_ALARM_1
4 4 4
122 123 125
4
1408
125
CHANNEL_MISMATCH_ALARM_1
4
1408
125
RX_LINE_AIS_ALARM_1
4
1405
124
AISL_PER
4
1407
124
Agere Systems Inc.
59
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 26. APS Channel (K1 and K2) Register Summary (continued) Function Register Name (First Occurrence) LTE Receive Channel 1 Performance Monitoring (RO) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Nonservice-Affecting Persistency Alarm (RO) LTE Receive Channel 1 Performance Monitoring (RO) Register Bits Qty. 1st Addr (hex) 140B 1408 Page
Last Second AIS-L PM RDI-L Latched Alarm RDI-L Persistency
RX_LINE_AIS_PM_1 RX_LINE_RDI_ALARM_1
4 4
127 125
RX_LINE_RDI_PER_1
4
140A
127
Last Second RDI-L PM
RX_LINE_RDI_PM_1
4
140B
127
Line Data Communication Channel (D4--D12) The line data communication channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used as one 576 kHz message-based channel for operations, administration, and maintenance communication (OA&M). The bytes are extracted from each frame, buffered, and are output serially, MSB first, on the RLDCC_n pin. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0xFF is constantly output. The data is clocked out on the positive edge of RLD_CLK_n. The RLD_CLK_n clock is divided down from the internal data clock (622.08 MHz/1080), giving a frequency of 576 kHz and a duty cycle of roughly 50%. In STS-48 mode, each of the four RLDCC pins transmit the line data communication channel bytes for that channel. In STS-192 mode, only the RLDCC_1 pin transmits these bytes, while the other pins are set high. Synchronization Status (S1) The synchronization status byte is located in the first STS-1 of the STS-48 or STS-192 only, and is used to convey the synchronization status of a network element. The byte is extracted from each frame. A new value is only validated and stored in the S1 byte after it has been received eight consecutive times. Detection of a new validated byte is indicated by the latched S1 new byte alarm bit. The alarm is only generated when the value of the new validated byte is different from the value of the last validated byte. The validated synchronization status byte is also transmitted on the RFRMn pin for each channel when the RFRM output enable control bit is set high. The byte is serialized MSB first as a repeating 77.76 MHz Manchester encoded* 16-bit code that is interrupted once per frame by the frame sync pattern 00001111. While the data rate of the signal is 77.76 MHz, the output pin is driven with 622 MHz low-voltage differential drivers, synchronous to the corresponding R_CLKO_n clock. When the RFRM output enable control bit is set low (the default value), an 8 kHz clock is transmitted on the RFRMn pin.
CLK
RFRM 0 FRAMING PATTERN
5-8402(F)
1
1
0
0
Figure 6. Timing Diagram for RFRM
* A logic 0 is encoded as an upward transition at the bit center; a logic 1 is encoded as a downward transition at the bit center. Each Manchester encoded bit requires two clock cycles. The frame sync pattern is not Manchester encoded, and therefore each bit only requires one clock cycle.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
During AIS insertion due to LOS, LOF, SEF, or line AIS, a constant high signal is transmitted on the RFRMn pin, regardless of the RFRM output enable control bit. In STS-48 mode, each of the four RFRMn pins operates according to the functionality specified above. In STS-192 mode, only the RFRM1 pin transmits the validated synchronization status byte or the 8 kHz clock. Table 27. Synchronization Status (S1) Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) LTE Receive Channel 1 Provisioning (R/W) Register Bits Qty. 1st Addr (hex) 1408 Page
New Validated S1 Latched Alarm RFRM Output Enable Control Bit
RX_S1_NEW_BYTE_ RAW_INT_1 RX_FRM_EN_1
4
125
4
1400
122
STS-192 Line Remote Error Indication (M1) The line remote error indication (REI-L) byte is located in the third STS-1 of the STS-48 or STS-192 only (in order of appearance in the STS-192 signal), and is used to convey to the far end the number of errors detected using the line BIP-8 bytes (truncated at 255). The byte is extracted from each frame and the value added to an internal 21-bit counter. The value in the counter is transferred to the REI-L registers on the positive edge of the PM_CLK input, at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. Table 28. Line REI (M1) Register Summary Function Register Name (First Occurrence) LTE Receive Channel 1 REI-L Performance Monitoring (U) (RO) Register Bits Qty. 1st Addr (hex) 140D, 140C Page
Last Second REI-L Count
REI_L_REG_1_U/ REI_L_REG_1_L
4/ 4
127/ 127
Express Orderwire (E2) The express orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for voice communications between line entities. The byte is extracted from each frame, buffered, and then output serially, MSB first, on the REXPOW_n pin. During AIS insertion due to LOS, LOF, SEF (provisionable), or line AIS, 0x7F is constantly output. The data is clocked out on the positive edge of ROW_CLK_n. In STS-48 mode, each of the four REXPOW pins transmit the E2 byte for a channel. In STS-192 mode, only the REXPOW_1 pin transmits the E2 byte while the other pins transmit a constant 0x7F serial stream.
Receive STS Path Processor
This block is replicated four times. Each block accepts the data for one STS-48 channel and terminates the SONET/SDH path layer overhead, without terminating the full path layer (i.e., demapping the payload). It provides pointer interpretation, path overhead processing, and drop interface alignment (pointer generation) for any mix of valid STS payloads from 48 channels of STS-1 to one channel of STS-48c, or part of an STS-192c channel. The exact mix of payloads is determined automatically by hardware by examining the pointer bytes. The received payloads can be optionally compared to a software provisioned map using the software concatenation map registers in the microprocessor interface. Concatenated payloads must follow the basic position requirement specified in GR-256-CORE that concatenated payloads start on an STS-3 boundary (STS-1 payloads may start anywhere). Note that the terminology used is from SONET, although SDH is also supported. Agere Systems Inc. 61
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
The pointer interpretation, path overhead processing, and drop interface alignment functions are actually grouped on an STS-12 level. Thus, each path processor block contains four instances of each of these functions along with a TSI module to convert the input data into four STS-12 channels. Of the path overhead processing functions, however, path trace monitoring is supported on any single STS-1 in each STS-48. 1:4 Demultiplex TSI In order to demultiplex the STS-48 data stream into four valid STS-12 data streams, the bytes in the STS-48 data must be reordered. Table 20 on page 51 shows the STS-1 ordering at the input to the four demultiplexers. Table 29 shows the STS-1 ordering after the demultiplexers. Table 29. STS-12 Byte Ordering Time (Left to Right for Each STS-12 Channel) 1 13 25 37 49 61 73 85 97 109 121 133 145 157 169 181 4 16 28 40 52 64 76 88 100 112 124 136 148 160 172 184 7 19 31 43 55 67 79 91 103 115 127 139 151 163 175 187 10 22 34 46 58 70 82 94 106 118 130 142 154 166 178 190 2 14 26 38 50 62 74 86 98 110 122 134 146 158 170 182 5 17 29 41 53 65 77 89 101 113 125 137 149 161 173 185 8 20 32 44 56 68 80 92 104 116 128 140 152 164 176 188 11 23 35 47 59 71 83 95 107 119 131 143 155 167 179 191 3 15 27 39 51 63 75 87 99 111 123 135 147 159 171 183 6 18 30 42 54 66 78 90 102 114 126 138 150 162 174 186 9 21 33 45 57 69 81 93 105 117 129 141 153 165 177 189 12 24 36 48 60 72 84 96 108 120 132 144 156 168 180 192 STS-12 Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Receive Pointer Processor The STS pointer processor is used for phase absorption and frequency synchronization of SONET payload from one clock domain (the receive or line timing) to another (the drop interface timing). This is accomplished by three basic functions: pointer interpreter, elastic store, and pointer generator. The pointer interpreter extracts the SONET synchronous payload envelope (SPE) from the incoming data by interpreting the H1 and H2 pointer bytes of the line overhead. The SPE is then written to the elastic store. The pointer generator reads the SPE from the elastic store and regenerates the H1 and H2 pointer bytes. Since the pointer processor does not terminate the path, intermediate performance monitoring is performed (i.e., the path overhead is not modified). Pointer Interpreter Functions. The STS pointer interpreter interprets the H1 and H2 bytes for each incoming STS-1. The interpreter has four states: loss of pointer (LOP), alarm indication signal (AIS), normal (NORM), and concatenation indication (CONC). The state diagram is shown in Figure 7 on page 63.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
3XAIS CONC 3XCONC AIS
3X CO
AI 3X
S
RM NO DF 3X XN 1
8x IN VA LI D
8xINVALID 8XNDF NORM 3XNORM
5-8400(F)r.1
LOP
Figure 7. Pointer Interpreter State Machine Incoming pointers are categorized into one or more of the following categories: 1. Normal pointer. 2. New data flag (NDF) pointer. 3. Concatenation indicator. 4. AIS pointer. 5. Invalid pointer. Consecutive (and identical, in the case of normal) pointers in each category are counted and used to determine state transitions, as shown in Figure 7. When changing states, NORM, CONC, and AIS always take precedence over LOP (NORM, CONC, and AIS being mutually exclusive) if conditions indicate that two different transitions are possible. In NORM state, increments and decrements can be evaluated in either SONET or SDH modes on a per-STS-12 basis. The provisioning is done with the INT_SONET_SDH bit in the STS-12 pointer processor provisioning register, using the following rules:
s
In SONET mode, the 8 of 10 rule is used, where eight of the ten I and D bits must be correct for the pointer to be considered an increment or decrement. Register 0x3000 bit 4 should be set to 1 for this mode. In SDH mode, the 3 of 5 rule is used, where three of the five I bits and three of the five D bits must be correct for the pointer to be considered an increment or decrement. Register 0x3000 bit 4 should be set to 0 for this mode.
s
Also in NORM state, three identical normal pointers with an offset different from the currently validated offset, or a single NDF pointer with a valid offset will cause the new offset to become the validated offset. The SPE will then be extracted at the new offset.
Agere Systems Inc.
8xINVALID
3XNORM
3XCONC
NC
3XAIS
63
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Classification of invalid pointers depends on the state. In NORM state, any pointer that is not one of the following is considered invalid:
s s s s
Normal NDF with the offset equal to the currently validated offset. NDF set with a valid offset. AIS pointer (all ones). An increment or decrement where all ten I and D bits are correct.
In AIS state, any pointer that is not an AIS pointer is considered invalid. In CONC state, any pointer that is not a concatenation indicator or an AIS pointer is considered invalid. The pointer interpreter provides the following information:
s
AIS-P and LOP-P defect indications on a per-STS-1 basis: these are used to create the LOP-P and AIS-P alarms in the STS-1 channel path alarms register, whose persistency is shown in the AIS_P_PERS and LOP_P_PERS bits of the STS-1 path alarm persistency register, and the AIS_P_PM and LOP_P_PM alarms in the path overhead last second bin register. A per-STS-1 indication of CONC state (RECD_CONC_MAP).
s
Table 30. Pointer Interpreter Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 3000 Page
SONET/SDH Increment/ Decrement Evaluation Rules Received Concatenation Map AIS-P Latched Alarm AIS-P Persistency Last Second AIS-P PM LOP-P Latched Alarm LOP-P Persistency Last Second LOP-P PM
STS-12 Pointer Processor INT_SONET_SDH Provisioning, STS-1 #1 to STS-1 #12 (R/W) Received Concatenation Map RECD_CONC_MAP STS-1 #1 to STS-1 #12 (RO) STS-1 #1 Alarm Interrupt Status AIS_P (W1C) STS-1 #1 Alarm Persistency (RO) AIS_P_PERS STS-1 #1 PM Last Second AIS Indicators (RO) STS-1 #1 Alarm Interrupt Status LOP_P (W1C) STS-1 #1 Alarm Persistency (RO) LOP_P_PERS STS-1 #1 PM Last Second LOP Indicators (RO)
16
145
16 192 192 192 192 192 192
440F 3013 3015 3016 3013 3015 3016
163 147 148 148 147 148 148
Elastic Store Functions. The elastic store provides a 20-byte deep buffer for each STS-1 channel. The receive SPE bytes for each STS-1 are written into the store along with an indication of SPE phase. The bytes are then read out of the store using drop interface timing, under control of the pointer generator. If the receive and drop timing is synchronous, the elastic store will remain half filled with the write and read pointers 180 degrees (10 bytes) apart. Any difference in the rates, or pointer adjustments on the receive side, will cause the store to fill or empty. A phase comparator in the elastic store monitors the fill level of the store and generates a pointer adjustment in the pointer generator whenever the level crosses a minimum or maximum threshold. These thresholds are symmetrical around the half-fill point in the store and are selected to provide 5 bytes of uncertainty for the transport overhead, a 3-byte window for pointer adjustments, and 2 bytes of dead band. Thus, the elastic store will cause a pointer adjustment in the pointer generator when the path timing of the incoming STS-1 has drifted more than an average of 2 bytes from start-up conditions. 64 Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
The integrity of the elastic store is constantly monitored for overflow/underflow conditions. If either of these conditions is detected, the read and write pointers are reset and the ES_OVRUN bit in the corresponding STS-1 channel path alarms register is set. Table 31. Elastic Store Register Summary Function Register Name (First Occurrence) STS-1 #1 Alarm Interrupt Status (W1C) Register Bits Qty. 1st Addr (hex) 3013 Page
Elastic Store Overrun Alarm
ES_OVRUN
192
147
Pointer Generator Functions. The pointer generator monitors the elastic store and produces a new pointer to align the read data to the frame phase of the drop interface. The base value of the pointer is determined by the offset between the phase of the SPE in the read data and the drop frame indication (DFRM). This value is then modified by the following conditions:
s
An increment or decrement operation is performed whenever the elastic store indicates the phase difference between the read and write pointers exceeds a minimum or maximum threshold. No increment or decrement operation will be performed for three frames following any pointer change operation. A new pointer value is sent along with an NDF for one frame whenever the SPE phase suddenly changes position. A new pointer value is sent along with an NDF for one frame whenever an elastic store overflow or underflow occurs, causing the read and write pointers to be reset. An all ones pointer value is sent whenever the pointer interpreter indicates the channel is in LOP or AIS state, or when AIS insertion is enabled for the channel through the microprocessor interface. If the channel is the head of a concatenated payload, all STS-1 channels associated with the payload will also have AIS inserted. A new pointer value is sent along with an NDF for one frame following the termination of the all ones. An all ones pointer value is sent within 125 s of the interpreter receiving an all ones pointer (as per SONET objective O3-99). Bits 5 and 6 of H1 (the SS-bits in SDH) pass through from the pointer interpreter, except during AIS-P, when they are set to 11.
s
s
s
s
s
The output of the pointer generator is the SPE data and the H1, H2, and H3 bytes for each STS-1 processed. All other bytes in the SONET frames are defined by the receive payload drop interface. Pointer Generator Bypass Function. The pointer processor has the ability to bypass the pointer generator for use in applications where the line timing is passed on (i.e., through timing, in an OC-192 to OC-12 deMUX). This is achieved by pulling up the DRPBYP pin to VDD. When the pointer generator is bypassed, the output data is taken from the pointer interpreter instead of from the output of the pointer generator. In this case, receive timing will be used by the payload drop interface. Table 32. Pointer Generator Bypass Register Summary Function Register Name (First Occurrence) Chip Status (RO) Register Bits Qty. 1st Addr (hex) 0006 Page
DRPBYP Pin Readback Bit
DRPBYP
1
112
Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Receive TOH Transparency. A passthrough capability using software provisioning for the TOH on the line interface to/from the TOH on the equipment interface is provisioned for the receive direction when the device setup STS-192 mode. In this case, receive timing will be used by the payload drop interface. The receive direction has the option for full TOH transparency of just line overhead transparency with section overhead used for the normal proprietary drop I/F OH. This feature is enabled in software by setting the appropriate bits in the LTE transmit channel 1--4 provisioning (R/W) registers (0x1C00, 0x1D00, 0x1E00, and 0x1F00, respectively). TOH transparency feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. When this feature is enabled, both the transmit and receive sections will be provisioned to the same mode (i.e., the function cannot be set up differently in transmit and receive directions). A full description is found in the TOH Transparency section on page 85. This feature is available on a per STS-48 level. When TOH transparency is enabled, the PP will be bypassed on a per STS-48 level. See the Receive Pointer Processor section on page 62 for more information on how this mode affects the device. AIS Insertion Functions. The pointer interpreter decides when to insert AIS-P on output data. The conditions under which AIS-P is inserted are summarized in Table 33. The conditions are provisioned on a per-STS-12 basis in the STS-N pointer processor control (provisioning) register with the AUTO_AIS_DIS bit. Table 33. AIS-P Insertion Conditions Condition Interpreter AIS-P Interpreter LOP-P Software AIS Insert Register Receive (line) Clock Lost First STS-1 in STS-48/STS-192 Stream Receives a Valid Concatenation Indicator
1. AIS-P affects H1, H2, H3, and all SPE bytes.
AUTO_AIS_DIS Bit Value 0 1 0 1 NA NA NA
Output Data AIS-P1 Flow-Through AIS-P1 Flow-Through AIS-P1 AIS-P1 AIS-P1
The flow-through data, as indicated in the table, will be different based on whether the pointer generator is being bypassed--specifically, the H1, H2, and H3 bytes will be different. If the pointer generator is not bypassed, the H1, H2, and H3 bytes will be generated by the pointer generator and will be normal pointers with the last known offset. In pointer generator bypass mode, the H1, H2, and H3 bytes will be the same as those received by the pointer interpreter, and any downstream equipment will see the same defects as the pointer interpreter. Note: It is not recommended to set the AUTO_AIS_DIS bit unless in pointer generator bypass mode. This feature is intended to be used only in the pointer generator bypass mode. Concatenated STS-1s will follow the AIS insertion of the STS-1 at the head of the concatenation. Changes to concatenated STS-1s will take effect during the pointer bytes (H1, H2, and H3). Thus, when using software AIS insert on the first STS-1 in the concatenation, it will immediately begin sending AIS-P data and the rest of the concatenation will begin sending AIS-P data after the next pointer (as seen in the pointer interpreter). In addition, AIS-P can be inserted on any STS-1 within a concatenation individually by writing the appropriate bit in the software AIS insert register.
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Table 34. Path AIS Insertion Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 3000 Page
Disabling of AIS-P Insertion on AIS-P and LOP-P Defects Software AIS-P Insertion Control
STS-12 Pointer Processor AUTO_AIS_DIS Provisioning, STS-1 #1 to STS-1 #12 (R/W) STS-12 Pointer Processor PP_CH_SW_AIS_INS_n Maintenance, STS-1 #1 to STS-1 #12 (R/W)
16
145
16
3001
145
Concatenation. Each STS-1 position has its own state machine. When an STS-1 enters the CONC state, indicating receipt of validated concatenation indicators, it begins following all pointer operations indicated by the first STS-1 in the concatenation. Information is passed between STS-12 pointer processing blocks to facilitate concatenations up to STS-192c. This allows the TSOT0410G4 to automatically adjust to incoming concatenated payloads. An unsupported concatenation alarm and a concatenation mismatch alarm are created to indicate status of the received concatenated payloads. The unsupported concatenation alarm is asserted when the received concatenation map from the pointer interpreter contains concatenations that cross an STS-3 boundary, but do not start at an STS-3 boundary, because the pointer interpreter and pointer generator cannot process such concatenations correctly. The concatenation mismatch alarm is generated if an STS-1's concatenation state does not match the provisioned expect state for that STS-1 and the comparison is enabled. The expect values are provisioned in the software concatenation map registers and the comparisons are enabled (on an STS-1 basis) in the software concatenation mask registers. The unsupported concatenation alarms and concatenation mismatch alarms are both reported on an STS-12 basis. In order to find the offending STS-1(s), the corresponding received concatenation map register(s) must be read and examined. The unsupported concatenation map alarm will be reported in the STS-12 that contains the first STS-1 of the unsupported concatenation. In the received concatenation map and the software concatenation map, the first STS-1 in a concatenation is flagged with 0 and all other STS-1s in the concatenation are flagged with 1s. In the registers, the first STS-1 of the STS-12 is in the LSB and the STS-1s are in SONET order. Since only 12 STS-1s are reported in each register, the four most significant bits are ignored. For example, if a read of a received concatenation map register returns 0x0FB6 (binary xxxx 1111 1011 0110), this means that there is an STS-3c starting at the first STS-1 of that particular STS-12, and an STS-3c starting at position 4, and an STS-6c (or larger) starting at position 7. To determine if the last concatenation is larger than STS-6c, the concatenation map for the next STS-12 must be read. In order to check the software concatenation map against the received concatenation map, every STS-1 in the concatenation (including the first) should have the compare enabled with the appropriate compare enable bit.
Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 35. Concatenation Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 4413 4413 440F 4406 Page
Concatenation Mismatch STS-48 Channel Path Alarms 1 CONC_MAP_MMCH_1 Alarm (W1C) Unsupported STS-48 Channel Path Alarms 1 UNSUPP_CONC_MAP_1 Concatenation Alarm (W1C) Received Concatenation Received Concatenation Map RECD_CONC_MAP Map STS-1 #1 to STS-1 #12 (RO) Software Provisioned S/W Concatenation Map STS-1 SW_CONC_MAP Expected Concatenation #1 to STS-1 #12 (R/W) Map Provisioned Concatenation S/W Concatenation Mask STS-1 SW_CONC_MASK Map Compare Enable #1 to STS-1 #12 (R/W)
4 4 16 16
164 164 163 161
16
440B
162
Pointer Justification (Increment and Decrement) Binning. For performance monitoring purposes, there is a provision to accumulate last second pointer justifications for one STS-1 in each STS-12 pointer processor. On each positive edge of the PM_CLK input, the last second counts of received and generated increments and decrements are transferred to the appropriate registers. The STS-1 within the STS-12 that will be monitored is provisioned by setting the INT_INC_BIN bits to the SONET STS-1 number desired in the STS-12 pointer processor control (provisioning) register. Programming this register to an invalid value will stop accumulation of justification information, but will not clear any justifications already counted. All of the justification counters will saturate at a value of 2000 (decimal). This is the maximum number of justifications that can be performed in one second. Table 36. Pointer Justification Binning Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 3000 Page
Selection of STS-1 within STS-12 to Monitor Last Second Increments Received Last Second Decrements Received Last Second Increments Generated Last Second Decrements Generated
STS-12 Pointer Processor ProviINT_INC_BIN sioning, STS-1 #1 to STS-1 #12 (R/W) STS-12 Pointer Interpreter PM, PP_CH_INT_INC_PM Last Second Increments, STS-1 #1 to STS-1 #12 (RO) STS-12 Pointer Interpreter PM, PP_CH_INT_DEC_PM Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) STS-12 Pointer Generator PM, PP_CH_GEN_INC_PM Last Second Increments, STS-1 #1 to STS-1 #12 (RO) STS-12 Pointer Generator PM, PP_CH_GEN_DEC_PM Last Second Decrements, STS-1 #1 to STS-1 #12 (RO)
16
145
16
3002
145
16
3003
146
16
3004
146
16
3005
146
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Receive Path Overhead (POH) Processor This block accepts the payload mapping information, status, and timing from the receive pointer interpreter, and extracts the path overhead from up to 12 STS channels. The extracted overhead is then stored internally and may be further processed for alarm or performance monitoring purposes. While an STS channel is in AIS or LOP status, all path overhead processing for the channel is inhibited. The definition and associated storage or processing of each byte is detailed as follows. Path Trace (J1). The path trace (J1) byte is the first POH byte of each unconcatenated STS-1 and carries a repeating message. Path trace messages are 64-bytes long (ASCII, terminated) in SONET and 16 bytes long (E.164) in SDH systems. The POH processor supports extraction of one path trace message per STS-48. There are four path trace extraction message buffers. In STS-192 mode, there are four path trace extraction message buffers--one for each of the STS-48 streams contained within the STS-192. The content of the message is either monitored for a mismatch from a provisioned expected message or monitored for a sustained change (validation) in the received message. If the message mode control bit is set to the provisioned mode, then the incoming message is compared against the software programmed expected message. The expected message is stored in internal memory for each STS-48 channel. A mismatch is declared if the received message differs from this expected message for ten consecutive messages. The mismatch clears when four out of five received messages match the expected message (fixed windowing is used for clearing). If the message mode control bit is set to the validated mode, the incoming message is monitored for a sustained change. A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message, is stored in internal memory, and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). The message mismatch state or the new (sustained) message state are reflected by maskable latched alarm bits in the STS-48 channel path alarms register. For path trace processing, provisioning of the selected STS-1 within the STS-48, SDH, or SONET message type, and validated or provisioned message mode is done using the STS-48 channel path trace control register. The expected messages for the four STS-48 channels are provisioned through the microprocessor interface using the path trace access control and 64-byte message buffer registers. This message buffer is also used to read the contents of the expected/stable or received messages from the internal message memories for all channels. The STS-48 channel and message type (expected/stable or received), and the access type (read/write) are specified using the path trace access control register. Once this register is configured, the actual access is triggered by writing a 0x0001 value to the path trace access start register. The transfer from internal memory to the message buffer is performed on the next message boundary. Completion of the access is indicated by the path trace access complete status register. Internally, for each STS-48 channel, a memory is used to store the currently received path trace message as well as the stable or provisioned message. The operation of the memory is monitored using parity, and any errors are reported using the J1 parity error alarm bit.
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Data Sheet May 2003
Functional Description (continued)
Table 37. J1 Register Summary Function Register Name (First Occurrence) STS-48 Channel Path Trace Control (R/W) STS-48 Channel Path Trace Control (R/W) STS-48 Channel Path Alarms 1 (W1C) STS-48 Channel Path Alarms 1 (W1C) Path Trace Buffer Word #1--Word #32 Path Trace Access Control (R/W) Path Trace Access Start Path Trace Access Complete Status (W1C) STS-48 Channel Path Alarms 1 (W1C) Register Bits Qty. 1st Addr (hex) 4406 4406 4413 4413 4110 4100 4102 4101 4413 Page
Message Type Select Message Mode (Provisioned or Validated) Message mismatch Latched Alarm New Message Latched Alarm J1 Access Message Buffer Message Buffer Access Control Message Buffer Access Start Message Buffer Access Complete Flag Buffer Parity Error Latched Alarm
TYPE_SEL MODE_SEL J1_MSG_MMCH J1_NEW_MSG J1_UP_BUFFER All Bits J1_AXS_START J1_AXS_DONE J1_BUF_PAR_ERR
4 4 4 4 32 1 1 1 4
161 161 164 164 154 154 154 154 164
Path BIP-8 (B3). The path BIP-8 byte carries the even parity of the data in the previous STS SPE frame (783 bytes for STS-1, M x 783 for STS-Mc). During every frame, the received B3 value is extracted and compared to the calculated BIP-8 for the previous frame. Detected errors are accumulated in an internal 16-bit counter based on either bit or block errors, as provisioned, per-channel. If bit error mode is enabled for the channel, each BIP-8 bit found to be in error causes the counter to increment. If block error mode is enabled for the channel, the counter only increments by one, regardless of the number of BIP-8 bits in error, provided that there are one or more bits in error. The control bit for counting bit or block errors is in the per STS-1 path overhead provisioning register. The value of the internal counter is transferred to the per STS-1 last second CV-P (path coding violation) count register on the positive edge of the PM clock input, at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. In addition to the CV-P counter, path BIP-8 errors are also tracked in a signal fail (SF) counter. Individual STS-1s have a 9-bit counter. Concatenated payloads have a 14-bit counter. This counter is used to detect SF defects for protection switching. An SF defect is detected when the error count reaches a selected threshold within a fixed window of time (typically representing a BER of 10-N, where N = 3 to 5), where the error count is cleared at the end of the time window. The defect is then cleared when the error count within a full time window is less than a threshold, where both the window and threshold represent a BER that is 1/10th the detection BER. The time windows and thresholds used are provisionable on a per-channel basis from eight pairs of common registers. Each pair of common registers represents the detection and clearing values for a particular payload type (i.e., STS-1, STS-3c, etc.) and BER threshold. Each register includes 2 bits to select one of four common-time windows and either 9 or 14 bits to select an error threshold. Two of the pairs of registers are reserved for STS-1 payloads and only support 9-bit thresholds, while the remaining six pairs support STS-Nc payloads. While a channel does not have an SF defect, the detection register of the pair defines the error threshold and time window. When a channel detects an SF defect, it switches to the clearing register to define the error threshold and time window. The four common-time windows each support a 16-bit value that represents the time window in 0.5 ms units.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Note that the time windows are continually cycling. Thus, the clearing time window for an STS-1 that has declared SF does not necessarily start at the exact time that SF is declared. The same can be said for the detect time windows. Also, when a new value is programmed into a time window register, it does not take effect until the end of the current window. Essentially, the eight pairs of threshold registers are intended to be used in groups of two, with each group representing two BER thresholds for a particular payload size. Thus, this facility supports separate working and protection channel SF defect BER thresholds for four payload sizes. This concept is demonstrated in Table 38, which shows the default powerup detection and clearing time windows and error limits for the common threshold registers, along with the payload sizes and BER thresholds they correspond to. Table 39 shows the default powerup values for the four common-time windows. Detection of an SF defect for a channel is indicated by the SIG_FAIL bit in the appropriate STS-1 channel path alarms register and causes a code to be sent in the E1 and F1 overhead bytes for that channel on the drop interface. SD defect detection is not supported in hardware; however, a control bit is provided (SD_INSERT in the path overhead maintenance STS-1 register) for each channel to force an SD defect code to be sent in the E1 and F1 overhead bytes for that channel on the drop interface. Table 38. BER Threshold Time Window and Error Limits for Path SF Detection Payload Size1 STS-1 STS-3c STS-6c STS-12c Register Set 0 1 2 3 4 5 6 7 BER Threshold 1 x 10-4 1x 1x 1x 10-5 10-4 10-5 Detection Window 1 2 1 2 1 2 1 2 Detection Error Limit 207 222 563 690 931 1374 1309 2658 Clearing Window 2 3 2 3 2 3 2 3 Clearing Error Limit 275 277 779 795 1496 1560 2824 3068
1 x 10-4 1 x 10-5 1x 1x 10-4 10-5
1. Measurements for STS-48c and STS-192c are not realistic. Refer to SONET/SDH specifications for details.
Table 39. Time Window Sizes for Path SF Detection Time Window 0 1 2 3 Length (in ms) 5 50 500 5000 Register Value 10 100 1000 10000
To set up an SF threshold, select one of the signal fail window size registers for the detect window and write the appropriate value to it. Select another signal fail window size register for the clear window (if different from the detect window) and write the appropriate value to it. Next, select a threshold register set (0--7) and write the detect threshold into the corresponding signal fail detect threshold register, using the two most significant bits of the register to choose the detect time window as chosen earlier. Then, write the clear threshold into the corresponding signal fail clear threshold register, using the two most significant bits to indicate the clear window as chosen earlier. Finally, for each STS-1 that is to use the new threshold, set the SF_THRESH_SEL bits in the path overhead maintenance STS-1 register to the number of the register set that has just been set up.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
As soon as SF is declared, the counters immediately switch to the clearing window, so it is only at the end of the current running clear time window that path BIP-8 errors begin to be considered for the clearing of SF. This ensures that an entire clearing window is used for clearing SF. Any STS-1 that does not belong to a concatenation has only a 9-bit counter. Thus, if a 14-bit clear threshold that is greater than 511 is used for such an STS-1, any SF defect is cleared at the end of the current clear time window, since the clear threshold can never be reached. To disable SF detection, a window of the smallest possible size (0.5 ms) can be set up and used with a detect threshold of more than 32, since a maximum of 32 B3 errors can be detected in 0.5 ms. Table 40. B3 Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 3010 3017 3011 3011 4002 Page
Bit or Block Error Counting Control Last Second CV-P Signal Degrade E1/F1 Code Insertion Control Signal Fail Register Set Selection Control Signal Fail Detection Threshold and Window Select Signal Fail Clear Threshold and Window Select Signal Fail Window Size Control Signal Fail Latched Alarm
STS-1 #1 Path Overhead CNT_BLK_ERRS 192 Provisioning (R/W) STS-1 #1 Last Second CV-P PM_STS1_CVP_CNT 192 Count (RO) STS-1 #1 Path Overhead SD_INSERT 192 Maintenance (R/W) STS-1 #1 Path Overhead SF_THRESH_SEL 192 Maintenance (R/W) STS-1 Signal Fail Detect SF_STS1_DET_THRESH_n 8 Threshold, Window Size Select 0 (R/W) STS-1 Signal Fail Clear SF_STS1_CLR_THRESH_n 8 Threshold, Window Size Select 0 (R/W) Signal Fail Window Size 0 SF_WIN_SIZE_0 4 (R/W) STS-1 #1 Alarm Interrupt SIG_FAIL 192 Status (W1C)
146 148 146 146 150
4003
150
4012 3013
153 147
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Path Signal Label (C2). The path signal label byte is used to indicate either the type of payload carried in the STS SPE or the status of the payload. See Table 41 for label assignments. Table 41. STS Path Signal Label Assignments Code (Hex) 00 01 02 03 04 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE Content of the STS SPE Unequipped Equipped--nonspecific payload VT-structured STS-1 SPE Locked VT mode Asynchronous mapping DS3 VT-structured STS-1 SPE with 1 VTx payload defect (STS-1 w/1 VTx PD) STS-1 with 2 VTx PDs STS-1 with 3 VTx PDs STS-1 with 4 VTx PDs STS-1 with 5 VTx PDs STS-1 with 6 VTx PDs STS-1 with 7 VTx PDs STS-1 with 8 VTx PDs STS-1 with 9 VTx PDs STS-1 with 10 VTx PDs STS-1 with 11 VTx PDs STS-1 with 12 VTx PDs STS-1 with 13 VTx PDs STS-1 with 14 VTx PDs Code (Hex) 12 13 14 15 16 EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC Content of the STS SPE Asynchronous mapping for DS4NA Mapping for ATM Mapping for DQDB Asynchronous mapping for FDDI Mapping for HDLC-PPP (proposed) STS-1 with 15 VTx PDs STS-1 with 16 VTx PDs STS-1 with 17 VTx PDs STS-1 with 18 VTx PDs STS-1 with 19 VTx PDs STS-1 with 20 VTx PDs STS-1 with 21 VTx PDs STS-1 with 22 VTx PDs STS-1 with 23 VTx PDs STS-1 with 24 VTx PDs STS-1 with 25 VTx PDs STS-1 with 26 VTx PDs STS-1 with 27 VTx PDs VT-structured STS-1 SPE with 28 VT1.5 payload defects, or a nonstructured STS-1 or STS-Nc SPE with a payload defect
Of the 256 possible values, only the codes 0x01 to 0x04 and 0x12 to 0x15 are currently defined to identify payload types, while the codes 0xE1 to 0xFC are defined to indicate payload defects (see Table 41). The valid payload specific codes are, by default, 0x02 to 0xE0, 0xFD, and 0xFE. The codes 0xE1 to 0xFC are used for indicating defects in the payload. The code 0xFF is a special reserved code due to its appearance in an STS AIS and is treated as a do not care during any defect detection or clearing. The C2 byte is extracted each frame and can be accessed from the per STS-1 path C2, RDI status register. The extracted C2 byte is also validated for five consecutive frames. If the locally provisioned value, configured in the per STS-1 path overhead provisioning registers, is any equipped value (i.e., not 0x00), the validated signal label is processed for the following listed defects.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
s
Payload Label Mismatch (PLM)--Detected if the validated signal label is a valid payload-specific code and does not match the provisioned expected signal label code in the per STS-1 path overhead provisioning register. Cleared if the extracted signal label, validated for five consecutive frames, matches the locally provisioned value, the equipped nonspecific code (0x01), the unequipped code (0x00), or a valid PDI code. If the locally provisioned value is the equipped nonspecific code, then it matches any equipped code (including PDI). Detection of a PLM defect is indicated by a maskable latched alarm bit in the per STS-1 channel path alarms register. The PLM alarm is also followed by a persistency register bit in the per STS-1 path alarm persistency register. Detection of a PLM defect causes a PLM-specific code to be sent in the E1 and F1 overhead bytes for that STS-channel on the drop interface. Path Unequipped (UNEQ)--Detected if the validated signal label matches the unequipped code (0x00). Cleared if the extracted signal label does not match the unequipped code for five consecutive frames. Detection of an UNEQ defect is indicated by a maskable latched alarm bit in the per STS-1 channel path alarms register and by a PM status bit in the per STS-1 path overhead last second bin register. The UNEQ alarm is also represented by a persistency register bit in the per STS-1 path alarm persistency register. Detection of an UNEQ defect causes a UNEQ-specific code to be sent in the E1 and F1 overhead bytes for that STS-channel on the drop interface; see the STS-12 Overhead Insertion and Scrambling section on page 77. Payload Defect Indication (PDI)--Detected if the validated signal label matches a valid PDI code. Codes 0xE1 to 0xFC are valid if the locally provisioned payload is VT-structured (0x02 or 0x03) or equipped nonspecific (0x01). Only 0xFC is a valid PDI code for other payload types which are not VT-structured. Cleared if the extracted signal label does not match a valid PDI code for five consecutive frames. PDI detection can be disabled by a control bit in the per STS-1 path overhead provisioning register. Detection of a PDI defect causes the PDI code to be sent in the E1 and F1 overhead bytes for that STS-channel on the drop interface; see the STS-12 Overhead Insertion and Scrambling section on page 77.
s
s
The scenarios presented by different expected and received (validated) signal label codes are presented in Table 42. Table 42. Path Signal Label (C2) Alarm Scenarios All C2 Code Values are in Hex 00 01 Provisioned C2 Byte 02, 03 04--E0, FD, FE E1--FB FC FF
1. If PDI-P detection is provisioned. 2. If extracted, validated C2 code = provisioned C2 code. 3. If extracted, validated C2 code provisioned C2 code.
Extracted C2 Byte (Validated Five Consecutive Frames) 00 [Unequipped] 01 [Equipped Nonsp] MATCH MATCH MATCH 02, 03 [VT-Structur ed] MATCH MATCH 2/ PLM-P3 PLM-P 04--E0, FD, FE E1--FB [VT PDI] FC [PDI] FF [AIS]
No Alarms UNEQ-P UNEQ-P UNEQ-P MATCH PLM-P MATCH2/ PLM-P3 Invalid Provisioning PDI-P1 PDI-P1 PLM-P1 PDI-P1 PDI-P1 PDI-P1 No Change No Change No Change
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Table 43. C2 Register Summary Function Register Name (First Occurrence) STS-1 #1 Path Overhead Status (RO) STS-1 #1 Path Overhead Provisioning (R/W) STS-1 #1 Alarm Interrupt Status (W1C) STS-1 #1 Alarm Persistency (RO) STS-1 #1 Alarm Interrupt Status (W1C) STS-1 #1 Alarm Persistency (RO) STS-1 #1 PM Last Second Indicators (RO) STS-1 #1 Path Overhead Provisioning (R/W) Register Bits Qty. 1st Page Addr (hex) 3012 3010 3013 3015 3013 3015 3016 3010 147 146 147 148 147 148 148 146
Extracted C2 Byte Provisioned (Expected) C2 Value PLM Latched Alarm PLM Persistency UNEQ Latched Alarm UNEQ Persistency Last Second UNEQ PM PDI Detection Disable
RCV_C2_BYTE PROV_STS1_EXP_C2 PLM_P PLM_P_PERS UNEQ_P UNEQ_P_PERS UNEQ PDI_EN
192 192 192 192 192 192 192 192
Path Status (G1). The path status byte is used to convey the path termination status and performance back to the originating STS PTE. This allows the performance of the full-duplex path to be monitored from any single point along the path. Bits 1 to 4 are used as a remote error indication (formerly far-end block error, or FEBE), while bits 5--7 are used as a remote defect indication. The G1 byte is extracted from each frame and processed for the following functions:
s
Remote error indication (REI-P). Indicates the count of bit errors detected at the far-end STS PTE using the path BIP-8. The error count is a binary number from 0 to 8 (values above eight are invalid and are interpreted as zero) and is accumulated in an internal 16-bit counter based on either bit or block errors as provisioned per channel through the microprocessor interface. If bit error mode is enabled for the channel, the counter is incremented by the actual error count. If block error mode is enabled for the channel the counter is only incremented by one, when the error count is between 1 and 8, regardless of the actual value. The control bit for counting bit or block errors is in the per STS-1 path overhead provisioning register. The value in the counter accumulates until it is transferred to the per STS-1 last second REI-P count registers at the positive edge of the PM_CLK input, at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. Remote defect indication (RDI-P). Indicates the detection of a defect at the far-end STS PTE. Initially, RDI-P was defined as a 1-bit value in bit 5, but has since been expanded to a 3-bit enhanced value (ERDI-P). Table 44 on page 76 shows the valid codes and interpretation for both the 1-bit and enhanced RDI schemes. As can be seen, bits 6 and 7 are always set to opposite values for ERDI while they are set to the same value for 1-bit RDI. The POH uses this fact to determine which RDI scheme is being used on a per STS basis. An RDI-P defect is then detected if a valid defect code for one of the RDI schemes is received for ten consecutive frames. The RDI-P defect is cleared when the no defects code for that scheme is received for ten consecutive frames. Any validated RDI-P defect is indicated by a maskable latched alarm bit in the per STS-1 channel path alarms register. Any validated 3-bit RDI code extracted is stored in the per STS-1 path C2, RDI status register. The RDI alarm is also followed by a persistency register bit in the per STS-1 path alarm persistency register. In addition, there are 4 PM status bits to report decoded RDI in the per STS-1 path overhead last second bin register, which are updated at the positive edge of the PM_CLK input.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 44. RDI-P Codes and Interpretation G1[5:7] 0xx1 1xx1 0012 0102 1012 1102 Priority of Enhanced RDI-P Codes Not Applicable Not Applicable 4 3 1 2 Trigger No Defects AIS-P, LOP-P No Defects PLM-P, LCD-P AIS-P, LOP-P UNEQ-P, TIM-P Interpretation No RDI-P Defect 1-bit RDI-P Defect No ERDI-P Defects ERDI-P Payload Defect ERDI-P Server Defect ERDI-P Connectivity Defect
1. These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 6 and 7 must be set to the same value, and should be set to 00. 2. These codes are transmitted by STS PTE that support enhanced RDI-P.
Table 45. G1 Register Summary Function Register Name (First Occurrence) STS-1 #1 Path Overhead Provisioning (R/W) STS-1 #1 Last Second REI-P Count (RO) STS-1 #1 Alarm Interrupt Status (W1C) STS-1 #1 Path Overhead Status (RO) STS-1 #1 Alarm Persistency (RO) STS-1 #1 PM Last Second Indicators (RO) Register Bits Qty. 1st Addr (hex) 3010 3018 3013 3012 3015 3016 Page
Bit/Block Error Counting Selection Last Second REI-P Count RDI-P Latched Alarm Validated 3-bit RDI-P Code RDI-P Persistency Last Second RDI-P PM
CNT_BLK_ERRS
192
146 148 147 147 148 148
PM_STS1_REIP_CNT 192 RDI_P RCV_RDI_CODE RDI_P_PERS RDI_ONE_BIT ERDI_PYLD ERDI_CONN ERDI_SRVR 192 192 192 192
Receive Payload Drop Interface
This block is replicated four times. Each block accepts four STS-12 data streams from the path processor and converts them to four 1-bit wide STS-12 serial streams at 622 MHz. The data is formatted as an STS-12 signal; however, most of the transport overhead bytes are either unused or are used for proprietary purposes. Framing, BIP-8 parity, and alarm status are inserted into the TOH bytes of each STS-12, and then the data is optionally scrambled. Each STS-12 data stream is output as a 1-bit wide 622 MHz serial stream. The four 1-bit wide serial STS-12 data streams are output along with a single 1-bit wide control output that carries timing information for all four of the data outputs.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
STS-12 Overhead Insertion and Scrambling The payload drop interface uses several of the TOH bytes to pass information to the payload device. All unused bytes have all zeros inserted in them. After the overhead bytes are inserted, all bytes in the STS-12, except the framing bytes, are scrambled with the SONET standard 1 + x6 + x7 algorithm, unless scrambling is disabled (for all STS-12 links) through the scrambling disable bit in the receive drop STS-48 channel n provisioning register. The bytes used, and their functions, are described as follows:
s s
A1 and A2 positions: carry normal STS-12 framing. J0 position: inserted in the first STS-1 of each STS-12 only, and carries an 8-bit provisionable ID value for the STS-12. This value is specified in the J0 trace--STS-12 channel n register. B1 position: inserted in the first STS-1 of each STS-12 only, and carries a BIP-8 calculated for all of the bits in the previous frame. As per the section BIP definition in GR-253, the BIP-8 is calculated on the scrambled data and then inserted in B1 for the next frame, before the byte is scrambled. Errors can be inserted in the B1 bytes of all STS-12 links through the BIP-8 error insertion bit in the receive drop STS-48 channel n provisioning register. E1 and F1 positions: inserted in each STS-1 and carry path level alarms for that STS channel. Both bytes carry the same 6-bit value, which encodes the path alarm information, as shown in Table 46.
s
s
Table 46. Path Alarm Information Encoding E1/F1 Value 00111111 11111111 00111110 00111101 00111100-- 00100001 00011111 00011110 00000000
s
Definition Loss of pointer or path AIS. Concatenation mismatch or software AIS insertion. Unequipped signal label. Signal fail (SF). PDI code 28 to PDI code 1. Signal degrade (SD). Payload label mismatch. No alarms.
D1, D2, and D3 positions: inserted in the first STS-1 of each STS-12 only and carry a 192 kHz data channel that is sourced by the RDDCCn (1 to 16) input, and is clocked on the positive edge of RDDCKn (1 to 4). K1 and K2 positions: inserted in both the first and second STS-1 of each STS-12. The first STS-1 carries the validated K bytes, while the second STS-1 carries the raw K bytes for the STS-48 or STS-192 that contained the STS-1 channel. The K bytes are extracted in the receive TOH processing block. See the APS Channel (K1 and K2) section on page 58. E2 position: inserted in the first STS-1 of each STS-12 only, and carries line level alarms for the STS-48 or STS-192 that contained the STS-12 channel. The bit assignments for the E2 byte are shown in Table 47 on page 78.
s
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Data Sheet May 2003
Functional Description (continued)
Table 47. Line Alarm Information Encoding E2 Value 00111 00110 00101 00100 00011 00000000 Definition Loss of Signal Loss of Frame Line AIS Signal Fail (SF) Signal Degrade (SD) No Alarms
Table 48. Drop Interface Overhead and Scrambling Register Summary Function Register Name (First Occurrence) Receive Drop STS-48 Channel Provisioning Register 1 (R/W) J0 Trace--STS-12 Channel 1 (R/W) Receive Drop STS-48 Channel Provisioning Register 1 (R/W) Register Bits Qty. 1st Addr (hex) 2400 2401 2400 Page
Scrambling Disable Control Section Trace (J0) ID Value B1 Error Insertion
SCRM_DISABLE J0_BYTE_n B1_ERROR_INS
4 16 4
137 137 137
Drop Interface Output Format Drop Data and Drop Clock. Each STS-12 data stream is output as a 1-bit wide 622 MHz serial stream. The 622 MHz clock is internally generated with a PLL whose reference is the 77.76 MHz D_CLK input (or the R_CLKn that corresponds to the STS-48 in which the STS-12 belongs, if drop alignment is bypassed). DCTL Outputs. In addition to the four STS-12 data streams, a 1-bit wide control signal (DCTL_[1--4]) that supplies timing enables for the data streams is output. These timing enables are encoded using a 2-bit vector for each byte of each STS-12. Thus, there is one byte of timing control for each byte of data from the four STS-12 streams. This byte of timing control is then scrambled using the standard 1 + x6 + x7 algorithm, passed to a high-speed multiplexer module, and output at 622 MHz synchronized to the STS-12 data as shown in Figure 8 on page 79. The encoding of the timing enable bits is shown in Table 49 on page 79. The DCTL_[1--4] outputs may be used by other devices that terminate the SPE path, such as external data engines. By using the DCTL codes, the SPE can be extracted from the output data without the need for another pointer interpreter inside the path terminator. The path overhead and payload can be separated as well. These outputs may be left unconnected if not used. DFRM. The frame alignment is determined by the DFRM input, which is synchronous to the D_CLK input, and is determined from the rising edge of the DFRM if it remains high for at least four D_CLK edges. Therefore, DFRM can be an 8 kHz clock or frame pulse meeting the minimum requirement of being high for four D_CLK edges. The beginning of the first A1 byte on each of the STS-12 outputs occurs approximately nine D_CLK cycles after the rising edge of DFRM.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
STS-12 CHANNEL 1
STS-12 CHANNEL 1 BYTE N
STS-12 CHANNEL 1 BYTE N + 1
... ... ... ...
STS-12 CHANNEL 2
STS-12 CHANNEL 2 BYTE N
STS-12 CHANNEL 2 BYTE N + 1
STS-12 CHANNEL 3
STS-12 CHANNEL 3 BYTE N
STS-12 CHANNEL 3 BYTE N + 1
STS-12 CHANNEL 4
STS-12 CHANNEL 4 BYTE N
STS-12 CHANNEL 4 BYTE N + 1
TIMING ENABLES
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 1
...
5-8407(F)r.1
Figure 8. STS-12 Data Outputs and Timing Table 49. Timing Enable Bit Definitions Timing Enable Bits 00 01 10 11 Definition TOH bytes SPE bytes POH bytes J1 byte
All control bytes follow this format, except the A1, A2, and B1 bytes in the section overhead. The A1 and A2 bytes carry the standard nonscrambled STS framing, while the B1 byte carries a BIP-8 calculated for all bytes in the previous frame after scrambling. If any STS-1 channel has AIS inserted in it by the path processor, the timing enables for that channel will always indicate a nominal SPE (i.e., no stuffs) with POH in column 4 and no J1 byte. Data Path Parity The receive payload drop interface terminates the internal data path including 1 bit of parity that is added to every byte of STS-48/STS-192 data through the device. This parity bit is compared to the calculated parity of the data path, and parity errors are reported in the corresponding bit in the receive drop STS-48 channel nonservice-affecting alarm register. Table 50. Receive Data Path Parity Register Summary Function Register Name (First Occurrence) Receive Drop STS-48 Channel Nonservice-Affecting Alarm (W1C) Register Bits Qty. 1st Addr (hex) 2405 Page
Data Path Parity Latched Alarm
RX_DATA_PAR_ ERR_n
4
138
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Regenerator Loopback (STS-192 Mode Only)
This feature is software provisioned to set up a regenerator loopback mode that loops back receive data and overhead towards the transmit line interface. When this feature is enabled, the transmit clock is derived from the receive clock at the 622 MHz level external to the device. The add interface buffers align the data between the receive and transmit clock domains. The TFRM signal is replaced by receive frame timing using the new add interface self sync option to transfer from the receive to the transmit clock domains. The option is enabled in software by setting the appropriate bit, REGEN_LOOPBACK, in the LTE transmit channel 1--4 provisioning (R/W) registers (0x1C00, 0x1D00, 0x1E00, and 0x1F00, respectively). The appropriate bit definitions are shown in Table 52. This mode will only function correctly when the device is in STS-192 mode. It will not work in STS-48 mode, since the four STS-48 streams need to be aligned through the transmit side. Four received STS-48 streams are unlikely to be aligned to the same clock and frame alignment. The REGEN loopback control from channel 1 will enable this mode for all four STS-48 channels when in STS-192 mode. The appropriate per-STS-48 transmit line AIS insert control will be active during receive LOS, receive LOF, or R_CLK failure while in regenerator loopback. Table 51. LTE Transmit Channel Registers--Regenerator Loopback Summary Function Register Name Register Bits Qty. 1st Addr (hex) 1C00 Page
Regenerator Loopback Enable
LTE Transmit Channel 1 Provisioning (R/W)
REGEN_LOOPBACK
4
130
Table 52. Regenerator Loopback Bit Definitions Bit 8 0 1 Definition Powerup default. Regenerator loopback--drop data looped back to add side.
Transmit Payload Add Interface
This block is replicated four times. Each block accepts four 1-bit wide STS-12 serial streams at 622 MHz and converts them to STS-48 data. This conversion is performed in three stages. In the first stage, each STS-12 has framing recovered, is optionally descrambled, and has certain TOH bytes processed. In the second stage, each STS-12 is passed through a buffer to synchronize the data to the common transmit clock and frame. Finally, in the third stage, the four STS-12 data streams are multiplexed into a single STS-48 data stream. This multiplexing is performed by a time-slot multiplex (TSM) module that reorders the bytes in the STS-12 data streams to provide a correctly ordered STS-48 data stream.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
STS-12 Framing, Descrambling, and TOH Processing As the transmit TOH processor overwrites all of the TOH bytes in all STS channels, the payload add interface uses several of these TOH bytes to receive information from the payload device. The bytes used, and their functions, are described as follows:
s
A1 and A2 positions: carry normal STS-12 framing. The payload add interface recovers framing for each of the STS-12 data streams and uses it to frame and byte align the STS-12 data word. In addition to byte alignment, the frame timing is also used to descramble all bytes in each STS-12, except the framing, using the SONET standard 1 + x6 + x7 algorithm (unless descrambling is disabled for all STS-12 links, through the transmit add STS-48 channel provisioning register). Once in-frame, an out-of-frame (OOF) defect is detected when two consecutive errored framing sequences are received. The detection of an OOF defect is indicated by a latched alarm status bit in the transmit add STS-48 channel n alarm register, and causes AIS to be inserted in all affected STS-1 channels. J0 position: present in the first STS-1 of each STS-12 only, and carries an 8-bit ID value for the STS-12. This value is extracted and stored in the J0 status register. B1 position: present in the first STS-1 of each STS-12 only, and carries a BIP-8 calculated for all bits in the previous frame. As per the section BIP definition in GR-253, the BIP-8 is calculated on the scrambled data, and then compared to the B1 in the next frame after the byte is descrambled. Any errors detected will cause the BIP-8 error latched alarm status bit to be set in the transmit add STS-48 channel alarm register. Detection of BIP errors is inhibited while the STS-12 is OOF, and for one frame following reframe. E1 and F1 positions: present in each STS-1 and carry path AIS insertion control for that STS channel. Both bytes carry the same value which encodes the path AIS insertion control as shown in Table 53. An AIS insertion request in either byte will cause AIS to be inserted in that channel and will set a read-only status bit in the AIS insert status register.
s
s
s
Table 53. Path AIS Insertion Encoding E1/F1 Value 00111111 00000000
s
Definition Path AIS Insertion No Alarms
D1, D2, and D3 positions: present in the first STS-1 of each STS-12 only, and carries a 192 kHz data channel that is serialized, and then output, on the TDDCCn (1 to 16) pin on the positive edge of TADCK. While the STS-12 is OOF, an HDLC abort (0x7F) is continually sent. K1 and K2 positions: present in both the first and second STS-1 of each STS-12. The first STS-1 carries validated K bytes, while the second STS-1 carries raw K bytes that can be optionally inserted in the TOH bytes of the STS-48 or STS-192, that contain that STS-12 channel as their first STS-12 of data. While the STS-12 is OOF, the K1 values inserted in the TOH bytes are inverted in each frame to cause a downstream APS failure, while the K2 values are held. E2 position: the transmit add interface does not process the E2 byte.
s
s
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 54. Add Interface Overhead and Scrambling Register Summary Function Register Name (First Occurrence) Transmit Add STS-48 Channel Provisioning (R/W) Transmit Add STS-48 Channel Alarm (W1C) J0 Status Register--1 (RO) Transmit Add STS-48 Channel Alarm (W1C) AIS Insert Status Register, STS-12 Channel #1 (RO) LTE Transmit Channel 1 Maintenance (R/W) Register Bits Qty. 1st Addr (hex) 2C00 2C09 2C01 2C09 2C05 1C01 Page
Descrambling Disable OOF Latched Alarm Section Trace (J0) ID Value B1 Error Latched Alarm E1/F1 AIS Insertion Status K1K2 Insertion Into Line TOH Control
DESCRM_DISABLE OOF_1 J0_BYTE--STS-12 Channel 1 B1_ERROR_1 AIS_INSERT_n TX_K_BYTES_ SELECT_1
4 4 16 4 16 4
139 142 139 142 140 131
Transmit Synchronization Buffer Each STS-12 data stream recovers its own clock and possesses a slightly different frame phase. The purpose of this buffer is to synchronize the STS-12 data to the common transmit clock and frame phase. Note, however, that it is only intended to compensate for a phase offset between the STS-12 data stream and the transmit timing. It will not compensate for a frequency offset. Any frequency offset will eventually cause a buffer overflow/underflow, which is indicated by a latched status bit in the transmit add STS-48 channel alarm register. The buffer is also only intended to compensate for 75 ns of delay skew between the STS-12 data stream and the transmit frame phase. Any additional phase offset, which must be common to all STS-12 data streams, can be compensated using the transmit frame offset feature described in Add Interface Framing (A1 and A2). Since the detection of a buffer overflow/underflow is asynchronous in nature, the transmit add STS-48 channel provisioning register contains a force add buffer overflow bit which allows testing of the add buffer overflow alarm bit. Table 55. Transmit Synchronization Buffer Register Summary Function Register Name (First Occurrence) Transmit Add STS-48 Channel Provisioning (R/W) Transmit Add STS-48 Channel Alarm (W1C) Register Bits Qty. 1st Addr (hex) 2C00 2C09 Page
Force Add Buffer Overflow Control Buffer Overflow Latched Alarm
FRC_ADD_BUFFER _OVRFLW ADD_12_BUFFER_ OVRFLW_1
4 4
139 142
Add Interface Framing (A1 and A2) The STS framing bytes are present in all STS-1 time slots of the STS-48 or STS-192. When normal framing is selected, the A1 bytes are set to 0xF6, while the A2 bytes are set to 0x28. If enhanced framing is selected, using the framing mode control bit, the A1 and A2 bytes contain normal framing in odd STS-1 time slots and the inverse value in even STS-1 time slots. The add interface framer is a simplified SONET/SDH framer. It frames based on both the A1/A2 boundary and the repetitive nature of the boundary (that the A1/A2 boundary recurs every 810 x 12 bytes).
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
TFRM Framing Signal. The alignment of the generated frame is determined by the TFRM input signal and the value stored in the Tx frame offset register. The TFRM input provides a common frame reference for all add STS-12 data streams. The TFRM input is an 8 kHz signal and is sampled with the 622.08 MHz T_CLK. The frame position is at the rising edge of the TFRM signal when it has been low for at least 32 T_CLK clock periods and then stays high for at least 32 more (i.e., a 0000 1111 pattern). This transition should be present at approximately the average position of the start of the first A1 byte in all of the add interface STS-12 serial inputs. If the TFRM is not aligned to the input data, the frame position can be delayed by the value in the Tx frame offset register, specified in multiples of 12.86 ns (eight 622.08 MHz clock cycles), which produces the transmit frame timing reference. A value of zero specifies no delay and the maximum value for this register is 9719. This range is equivalent to advancing the frame timing reference over an entire STS-12 period. This offset is required to align the transmit frame position with the frame position of the add STS-12 data streams as described in the Transmit Synchronization Buffer section on page 82. If the TFRM rising edge should jitter with respect to the 622.08 MHz T_CLK, jitter on the TFRM input can be compensated for up to 16 T_CLK cycles from the starting position without affecting the generated frame position. This compensation is enabled with the TX_FRM_DEJITTER_EN bit in the LTE transmit provisioning register. If the TFRM input drifts more than 16 T_CLK cycles from its starting position, the transmit frame position is realigned to the next TFRM frame position (plus any offset added in the offset register), and a TX_FRM_RESYNC alarm is produced. If the TFRM frame signal is not received at least once every eight frames (i.e., 1 kHz), TFRM synchronization loss is indicated in the TFRM LOF alarm bit. During TFRM synchronization loss, AIS-P is inserted as described in the STS Payload Pointer (H1 and H2) section on page 88. While frame synchronization, once established, could be continued by counting clock cycles, the requirement for the TFRM signal to be provided at least once every eight frames provides an important check on system function. The TFRM input is a required signal for the transmit side of the TSOT0410G4. Recovery of TFRM frame sync is described in the Synchronization Status (S1) section on page 91. Add Interface Self-Sync Option. The TFRM input can be obtained from the add interface through a self-sync option to provide a common frame reference for all add STS-12 data streams as an alternate to the TFRM input. The transmit add synchronization enable option provides for the use of the frame timing from one of the add pseudo STS-12 links as the transmit frame sync instead of TFRM. This option provides the frame sync from the add clock domain to the T_CLK clock domain. The option is enabled with the ADD_TX_SYNC (bit 15) in the LTE transmit common provisioning register. When the self-sync option is enabled, the frame is sampled and then the add interface free-runs until either the feature is disabled and reenabled, or when the ADD12 (out of frame on used link) or T_CLK failure alarm is set and clears. Therefore, when changing the ADD12 link, the feature should be disabled and then reenabled after the channel is changed. The add interface self-sync feature automatically resynchronizes when a buffer overflow/underflow is detected. This resyncing is inhibited if the selected ADD12 is out-of-frame. The resync function is implemented by resampling the selected ADD12 frame timing and using that to realign the buffer write pointer. The only limit to the resync property is that it only resamples the frame timing once after an overflow/underflow and there is no guarantee that the buffer is centered; i.e., if the clock drift continues after the overflow/underflow. When the ADD_TX_SYNC bit in the LTE transmit common provisioning is set to 1, the frame pulse will be derived from the add interface input. Bit 0 through bit 3 in the LTE transmit common provisioning register then select which add channel (1--16) the TFRM will be obtained from. Bits 4--14 are unused in that case. See Table 128 on page 128. The preferred method of provisioning the add interface self-sync option is to provision the ADD_TX_SYNC register with the selected channel first, and then in the next write, provision the ADD_TX_SYNC enable. Note: The add-sync option should be disabled before the regenerator loopback option is enabled. Enabling regenerator loopback before the add sync option can cause transmit timing to corrupt overhead bytes.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Table 56. Frame Pulse Provisioning Bit Definitions Bit 15 ADD_TX_SYNC 0 1 0 Bit 14 TX_FRM_DEJITTER_EN 0 0 1 Definition Reset default. Transmit add synchronization enabled. TFRM dejitter circuit enable.
Table 57. Transmit Framing Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit--Frame Pulse Offset Count (R/W) LTE Transmit--Frame Pulse Offset Count (R/W) LTE Transmit--Interrupt Alarm Register (W1C) LTE Transmit--Interrupt Alarm Register (W1C) LTE Transmit--Frame Pulse Offset Count Register Bits Qty. 1st Addr (hex) 1C00 1B00 1B00 1B05 Page
Enhanced Framing Mode Control Transmit Frame Offset Control Transmit Frame Dejitter Control Transmit Frame Resynchronization Latched Alarm TFRM Synchronization Loss Latched Alarm Transmit Add Synchronization Enable
TX_FRAMING_MODE_1 LTE_TX_FRM_OFFSET_COUNT TX_FRM_DEJITTER_EN TX_FRM_RESYNC
4 1 1 1
130 128 128 129
TX_FRM_LOF ADD_TX_SYNC
1 1
1B05 1B00
129 128
4:1 Time-Slot Multiplex (TSM) In order to multiplex the four STS-12 data streams into a valid STS-48 data stream, the bytes in the STS-12 data streams must be reordered. This reordering is needed due to the STS-N multiplexing rules, which require an STS-12 channel to be interleaved in 4-byte chunks.
Transmit Transport Overhead (TOH) Processor
This block is replicated four times. Each block accepts the data for one STS-48 channel from the transmit payload add interface, and inserts the transport section and line overhead. The inserted overhead is either sourced internally, or provided externally on serial inputs. If sourced internally, the overhead may be from registers in the microprocessor interface, or derived. In STS-48 mode, each channel carries complete transport overhead. In STS-192 mode, only the first STS-48 channel carries complete transport overhead, while the other channels only carry framing (A1, A2), Z0, and line BIP-8. In addition, the line overhead bytes can all be overwritten with all ones (along with all of the payload SPE bytes) by enabling line AIS insertion in the memory map.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
TOH Transparency The TOH transparency option provides a passthrough capability for the TOH on the line interface to/from the TOH on the equipment interface. When this feature is enabled, both the transmit and receive sections will be provisioned to the same mode (i.e., the function cannot be set up differently in transmit and receive directions). The transmit direction has the option for full TOH transparency or just line overhead (MSOH) transparency with section (RSOH) overhead insertion. The receive direction has the option for full TOH transparency or just line overhead transparency with section overhead used for the normal proprietary drop I/F OH. This feature is available on a per STS-48 level by setting the TOH transparency enabled bit and the line TOH transparency only enabled bit of the LTE transmit channel provisioning register. When TOH transparency is appropriately provisioned, the pointer processor will be bypassed on a per STS-48 level. If enabled, AIS insertion due to an E1/F1 code in the add TOH will be disabled. Enforcing AIS-L from the transmit side does operate even using full transparency. During full or line transparency, the only access to the OH bytes is through the TOHDAT interface. The microprocessor-based features that would modify the line or section overhead will not be available. If overhead bytes are inserted using the TOHDAT interface, a valid B1 must be inserted for full transparency and/or B2 for full or line transparency. The option is enabled in software by setting the appropriate bits, TOH_TRANS_EN and LINE_TRANS_ONLY_EN, in the LTE transmit channel 1--4 provisioning registers (0x1C00, 0x1D00, 0x1E00, and 0x1F00, respectively). The appropriate bit definitions are shown in Table 58. TOH transparency feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. Table 58. LTE Transmit Channel Registers--TOH Transparency Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit Channel 1 Provisioning (R/W) Register Bits Qty. 1st Addr (hex) 1C00 1C00 Page
TOH Transparency Enabled Line TOH Transparency Only Enabled
TOH_TRANS_EN LINE_TRANS_ONLY_EN
4 4
130 130
Table 59. TOH Transparency Bit Definitions Bit 7 LINE_TRANS_ONLY_EN X 0 1
Note: X denotes either state.
Bit 6 TOH_TRANS_EN 0 1 1
Definition Section and Line Terminated (pointer processor state dependent on DRPBYP pin). Full Section and Line Overhead Transparency (pointer processor is bypassed automatically). Line Overhead Transparency Section Is Terminated (pointer processor is bypassed).
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Transmit Overhead Serial Links In addition to the individual provisioning or external availability of the overhead bytes, the full set of transport overhead bytes for the STS-48 channel (1296 bytes) can be sourced serially using the TOHDAT_n_[1:0] pins. Insertion must be globally enabled in software, using the TOH data insert control bit, and then enabled on a per-byte basis by strobing the TOHEN_n pin high during the LSB of the byte to insert (the state of the TOHEN_n is ignored during the other bits). The bytes are received MSB first, with each pair of bits input on the positive edge of TOH_CLK_n (41.472 MHz). The location of the MSB bit of the first A1 byte is identified by the TOHFP_n output going high. For B1 and B2, the value received is actually used as an XOR corruption mask for the internally calculated values. In STS-48 mode, the TOHDAT_n_[1:0] pins, along with the TOHEN_n pin, capture the transport overhead for that STS-48 channel. In STS-192 mode, the four pairs of TOHDAT_n_[1:0] pins, along with their respective TOHEN pins, capture the entire STS-192 overhead (5184 bytes), where the TOHDAT_1 pins capture STS channels 1 through 48, and the TOHDAT_2, TOHDAT_3, and TOHDAT_4 pins capture STS channels 49 through 96, 97 through 144, and 145 through 192, respectively. The timing for this is described in the Transmit Overhead Serial Link section on page 180. Internally, a memory is used for each channel to buffer the data and transfer it between the external data rate and the internal data rate. The operation of the memory is monitored using parity and any errors are reported using the TOHDAT parity error alarm bit. This alarm bit is present in the LTE transmit channel n interrupt alarm register and is valid regardless of the mode (STS-48 or STS-192) in which the device is operating. When enabled, the overhead serial link takes precedence over all other overhead sources, with the exception of software enabled line or path AIS insertion or path unequipped insertion. Table 60. Transmit Overhead Serial Links Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit Channel 1 Interrupt Alarm (W1C) Register Bits Qty. 1st Addr (hex) 1C00 1C0C Page
Global TOH Data Insert Control TOH Buffer Parity Error
TX_TOH_DATA_INSERT_1 TX_OH_MEM_PARITY_ERR_1
4 4
130 133
Section Trace/Section Growth (J0/Z0) The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. The TOH processor supports insertion of either SONET 64-byte (ASCII, terminated) or SDH 16-byte (E.164) section trace messages. The message is stored in internal memory and should be repeated four times if a 16-byte SDH message is to be sent. The message is provisioned by software using the section trace access registers (see the Section Trace (J0) section on page 53 for details). After the message is provisioned, insertion of the message must be enabled through the J0 Msg insert control bit. If insertion is not enabled, the J0 byte is instead sent as 0x01 for STS-48 mode or 0xCC for STS-192 mode. The section growth bytes present in the remaining STS-1 locations of the STS-48 or STS-192 are set to the fixed pattern 0xCC in STS-192 mode, or to an increasing binary count (2 to 48, corresponding to order of appearance) in STS-48 mode. Internally, a memory is used to store four section trace messages, one for each channel. The operation of the memory is monitored using parity, and any errors are reported using the transmit J0 parity error alarm bit that is reported in the LTE transmit interrupt alarm register.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Table 61. Transmit Section Trace (J0) Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 1C01 1B05 Page
Section Trace Message Insert Enable Control J0 Memory Parity Error Section BIP-8 (B1)
LTE Transmit Channel 1 TX_J0_MSG_INSERT_EN_1 Maintenance (R/W) LTE Transmit--Interrupt TX_J0_MEM_PARITY_ERR Alarm Register (W1C)
4 1
131 129
The section BIP-8 byte is located in the first STS-1 of the STS-48 or STS-192 only, and carries the even parity of the scrambled data in the previous STS-192 frame. In every frame, the calculated BIP-8 for the previous frame is inserted in the B1 byte of the current frame prior to scrambling. The B1 value can be fully corrupted (by inverting all bits) on a per-channel basis, using the B1 corrupt enable control bit. The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames between rising edges of PM_CLK. The B1 corrupt frame count register specifies this duration and is shared between the four channels. Table 62. Transmit B1 Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit--B1 Corrupt Frame Count (R/W) Register Bits Qty. 1st Addr (hex) 1C00 1B01 Page
B1 Corrupt Enable B1 Corrupt Duration Control
B1_CORRUPT_EN_1 LTE_TX_B1_NUM_CORRUPT_ FRAMES
4 1
130 128
Local Orderwire (E1) The local orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for voice communications between regenerators, hubs, and remote terminals. The byte is input MSB first, on the TLCLOW_n pin, and is inserted in each frame. The data is clocked in on the positive edge of TOW_CLK_n. The TOWCKn clock is divided down from the section data communications channel clock, TSDCKn (192 kHz/3), giving a frequency of 64 kHz and a duty cycle of 33%. In STS-48 mode, each of the four TLCLOW pins input the E1 byte for that channel. In STS-192 mode, only the TLCLOW_1 pin inputs the E1 byte, while the other pins are unused. Section User Channel (F1) The section user channel byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for use by the network provider. The byte is input serially, MSB first, on the TSUSERn pin, and is inserted each frame. The data is clocked in on the positive edge of TOW_CLK_n. In STS-48 mode, each of the four TSUSER pins input the F1 byte for that channel. In STS-192 mode, only the TSUSER_1 pin inputs the F1 byte, while the other pins are unused.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Section Data Communications Channel (D1, D2, and D3) The section data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used as one 192 kHz message-based channel for operations, administration, and maintenance communication. The bytes are input serially, MSB first, on the TSDCC_n pin, and are inserted in each frame. The data is clocked in on the positive edge of TSD_CLK_n. The TSD_CLK_n clock is divided down from the line data communications channel clock, TLD_CLK_n (576 kHz/3), giving a frequency of 192 kHz and a duty cycle of 33%. In STS-48 mode, each of the four TSDCC pins input the section data communication channel bytes for that channel. In STS-192 mode, only the TSDCC_1 pin inputs these bytes, while the other pins are unused. STS Payload Pointer (H1 and H2) The STS payload pointer bytes are normally set to the values received at the transmit payload add interface. These values are overwritten under the following conditions (in order of precedence from highest to lowest):
s s
Line AIS: enabled using the AIS-L insert control bit. Unequipped signal insertion: enabled on a per STS-1 channel basis using the UNEQ-P insert enable registers; overwrites the pointer bytes (H1, H2) for that channel with 0x60 0x00 or 0x68 0x00, based on SS_MODE (see the SS Bits section below) and the SPE bytes with all zeros. Software AIS insertion: enabled on a per STS-1 channel basis using the path AIS insert enable registers; overwrites the pointer bytes for that channel with 0xFF 0xFF (H1 H2) and the SPE bytes with all ones. TFRM loss of frame sync: overwrites the pointer bytes in all STS-1 channels with 0xFF 0xFF (H1 H2) and all SPE bytes with all ones (AIS-P). TOHDAT insertion: enabled on a per STS-48 channel basis using the TOH data insert control bit; overwrites the pointer bytes with the data serially received on the TOHDAT_n_[1:0] pins if the TOHEN_n pin is high for H1 and H2.
s
s
s
The pointer bytes are also automatically overwritten with all ones in the transmit payload add interface under the following conditions:
s s
In all STS channels of an STS-12 due to an OOF on that STS-12 data input. For the affected STS channel due to a path AIS insert request received for that STS in the STS-12 overhead.
SS Bits. The SS bits in the STS payload pointer (H1 and H2) are provisioned using SS_MODE (bit 9) and TX_SS_OVERWRITE_EN (bit 10) in each LTE Tx channel provisioning register. The SS bit mode is set to 0 for SONET (00) or 1 for SDH (10) and defines the value of the SS bits for unequipped signal insertion. The SS bits mode also defines the value of the SS bits that are inserted in all of the outgoing H1 bytes for that OC-48 channel if the Tx SS bit overwrite feature is enabled. The SS bits are passed through untouched if the transmit SS bit overwrite feature is not enabled. The overwrite feature is disabled during AIS (line and path) insertion when TOHDAT insertion is enabled for that H1 byte or when the incoming H1 byte is 0xFF.
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Table 63. Transmit STS Payload Pointer Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Maintenance (R/W) LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 (R/W) LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 (R/W) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit Channel 1 Provisioning (R/W) Register Bits Qty. 1st Addr (hex) 1C01 1C02 Page
AIS-L Insert Control UNEQ-P Insert Control
TX_LINE_AIS_INSERT_1 LTE_TX_1_UNEQ_P_EN_1
4 16
131 131
Software AIS-P Insert Control TOH Data Insert Control Transmit SS Bit Overwrite Enable Control SS Bit Mode for Unequipped Signal Insertion Control Line BIP-8 (B2)
LTE_TX_1_PATH_AIS_EN_1
16
1C06
132
TX_TOH_DATA_INSERT_1 TX_SS_OVERWRITE_EN SS_MODE
4 4 4
1C00 1C00 1C00
130 130 130
The line BIP-8 is located in each STS-1 of the STS-48 or STS-192, and carries the even parity for the line overhead and SPE data in the previous STS-1 frame. Since the B2 byte is calculated for each STS-1, independent of the other STS-1s, the device mode (STS-48 or STS-192) does not affect the operation of this block. The B2 values in all STS-1s in an STS-48 channel can be fully corrupted (by inverting all bits) on a per-STS-48 basis using the B2 corrupt enable control bit. The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames between rising edges of PM_CLK. The B2 corrupt frame count register specifies this duration and is shared between the four channels. Table 64. Transmit B2 Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit--B2 Corrupt Frame Count (R/W) Register Bits Qty. 1st Addr (hex) 1C00 1B02 Page
B2 Corrupt Enable B2 Corrupt Duration Control
B2_CORRUPT_EN_1 LTE_TX_B2_NUM_CORRUPT _FRAMES
4 1
130 128
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Data Sheet May 2003
Functional Description (continued)
APS Channel (K1 and K2) The APS channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used for automatic protection switching (APS) signaling to coordinate line level protection switching. In addition, the K2 byte is also used to carry line AIS and line RDI signals. Both bytes are inserted during each frame, normally using either values stored in the K byte register, or using the raw or validated values received at the transmit payload add interface. The K byte select bits in the LTE transmit channel n maintenance register determine which source to use. This is outlined in Table 65. In addition, the value of bits 6--8 in K2 can optionally be automatically overwritten by 110 (RDI-L) when AIS-L, LOS, SEF, or LOF (SEF and LOF only if AIS insertion is enabled) are detected for the receive STS-48 or STS-192. This insertion is controlled by the RDI-L select bit in the LTE transmit channel n maintenance register. When RDI-L is triggered, it will be inserted for a minimum of 20 consecutive frames, regardless of the length of the receive defect. Table 65. K Byte Select Control Bits K Byte Select Value (Binary) 00 01 10 11 Source for K1K2 Insertion LTE transmit channel 1 K1K2 byte insert values register. Raw K1K2 byte from the transmit payload add interface. Validated K1K2 byte from the transmit payload add interface. Invalid. Do not program this value.
Table 66. Transmit APS Channel (K1K2) Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Maintenance (R/W) LTE Transmit Channel 1 K1K2 Byte Insert Values (R/W) LTE Transmit Channel 1 Maintenance (R/W) Register Bits Qty. 1st Page Addr (hex) 1C01 1C0A 131 132
K1K2 Source Control K1K2 Software Insert Value
TX_K_BYTES_SELECT_1 TX_K1_SW_BYTE_1 TX_K2_SW_BYTE_1 RDI_L_SELECT_1
4 4
RDI-L Insert Control
4
1C01
131
Line Data Communication Channel (D4--D12) The line data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used as one 576 kHz message-based channel for operations, administration, and maintenance communication (OA&M). The bytes are input serially, MSB first, on the TLDCCn pin, and are inserted in each frame. The data is clocked in on the positive edge of TLDCKn. The TLDCKn clock is divided down from the internal data clock (77.76 MHz/135), giving a frequency of 576 kHz and a duty cycle of roughly 50%. In STS-48 mode, each of the four TLDCC pins input the line data communication channel bytes for that channel. In STS-192 mode, only the TLDCC1 pin is used to input these bytes, while the other pins are not used.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Functional Description (continued)
Synchronization Status (S1) The synchronization status byte is located in the first STS-1 of the STS-48 or STS-192 only, and is used to convey the synchronization status of a network element. The byte is inserted in each frame using either a value provisioned in the S1 byte control register, or from a value received on the TFRM signal. The S1 byte insert control bit determines which of these two sources to use. The data on TFRM is clocked in on the positive edge of T_CLK, MSB first, as a repeating 77.76 MHz Manchester encoded 16-bit code that is interrupted once per frame by the frame sync pattern 00001111 (at 77.76 MHz). If the frame sync pattern is not received at least every eight frames (i.e., 1 kHz), a TFRM sync loss is indicated in the TFRM LOF alarm bit and the value 0x0F is used for S1 if insertion is enabled. During TFRM sync loss, AIS-P is inserted as described in the STS Payload Pointer (H1 and H2) section on page 88. The 8-bit (16 bits of Manchester) value received is then validated three times before being optionally inserted into the transport overhead as the S1 byte. This validated value is reflected in the TFRM S1 byte status register and if a value is not validated over the course of the frame, the TFRM S1 byte invalid alarm bit is set. This alarm bit, along with the TFRM LOF alarm bit, is found in the LTE transmit interrupt alarm register. Table 67. Transmit Synchronization Status (S1) Register Summary Function Register Name (First Occurrence) Register Bits Qty. 1st Addr (hex) 1C01 1C0B Page
S1 Source Control Provisioned S1 Byte
TFRM S1 Validated Value TFRM S1 Byte Invalid Latched Alarm
LTE Transmit Channel 1 S1_BYTE_TX_FRM_INSERT_1 Maintenance (R/W) LTE Transmit Channel 1 LTE_TX_1_S1_DATA_1 S1 Byte Insert Value (R/W) LTE Transmit--TFRM S1 LTE_TX_S1_BYTE_TX_FRM Byte (RO) LTE Transmit--Interrupt TX_FRM_S1_BYTE_INVALID Alarm Register (W1C)
4 4
131 132
1 1
1B04 1B05
129 129
STS-192 Line Remote Error Indication (M1) The line remote error indication (REI-L) byte is located in the third STS-1 of the STS-48 or STS-192 only (in order of appearance in the STS-192 signal), and is used to convey to the far end the number of errors detected in the receive direction using the line BIP-8 bytes. The byte is inserted each frame with a binary value indicating the number of line BIP-8 errors (truncated at 255) detected in the previous receive frame for the entire STS-48 or STS-192. The value of the byte can be fully corrupted (by setting all bits) on a per-channel basis using the M1 corrupt enable control bit. The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames between rising edges of PM_CLK. The M1 corrupt frame count register specifies this duration and is shared between the four channels. Table 68. Transmit M1 Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) LTE Transmit--M1 Corrupt Frame Count (R/W) Register Bits Qty. 1st Addr (hex) 1C00 1B03 Page
M1 Corrupt Enable M1 Corrupt Duration Control Agere Systems Inc.
M1_CORRUPT_EN_1 LTE_TX_M1_NUM_CORRUPT_ FRAMES
4 1
130 129
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Functional Description (continued)
Express Orderwire (E2) The express orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for voice communications between line entities. The byte is input serially, MSB first, on the TEXPOW_n pin and is inserted in each frame. The data is clocked in on the positive edge of TOW_CLK_n. In STS-48 mode, each of the four TEXPOW pins input the E2 byte for that channel. In STS-192 mode, only the TEXPOW_1 pin captures the E2 byte, while the other pins are unused.
Transmit STS-192 Line Interface
This block is hardware configured to accept four STS-48 streams and convert them to either a single 16-bit wide serial STS-192 stream at 622.08 MHz or four 4-bit wide serial STS-48 streams at 622.08 MHz. The conversion process is essentially the same for both output formats, except that for STS-192 mode, the four STS-48 channels must be passed through a time-slot multiplex (TSM) block first to multiplex them into a STS-192 data stream. The resulting STS-192, or each of the STS-48 streams, is then optionally scrambled, has section BIP-8 calculated for it, and is multiplexed up to a 622 MHz signal. Time-Slot Multiplexer (TSM) In STS-192 mode, the bytes in the four STS-48 channels need to be combined and reordered to create an STS-192 data stream. This is performed by the time-slot multiplexer (TSM). Table 20 on page 51 shows the input ordering to the TSM and Table 19 on page 51 shows the output ordering of the TSM. Scrambler The data stream is normally scrambled using the standard generator polynomial 1 + x6 + x7. The scrambling can be disabled by the corresponding transmit scrambler disable bit of the LTE transmit channel n provisioning register. Table 69. Transmit Line Scrambler Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Provisioning (R/W) Register Bits Qty. 1st Addr (hex) 1C00 Page
Scrambler Disable Control
SCRM_DIS_1
4
130
Data Path Parity The transmit line interface terminates the internal data path, including one bit of parity that is added for every byte of STS-48/STS-192 data through the device. This parity bit is compared to the calculated parity of the data path and parity errors are reported using the corresponding bit in the LTE transmit channel n interrupt alarm register. Table 70. Transmit Data Path Parity Register Summary Function Register Name (First Occurrence) LTE Transmit Channel 1 Interrupt Alarm (W1C) Register Bits Qty. 1st Addr (hex) 1C0C Page
Data Path Parity Error Latched Alarm 92
TX_DATA_PAR_ERR_1
4
133
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface
Architecture
The TSOT0410G4 microprocessor interface architecture is configured for glueless interface to two specific microprocessors, the Motorola (R) MPC860 and MC68360; however, other processors may also be utilized. Bus transfers using the MC68360 are asynchronous, while the MPC860 transfers are synchronous to the processor clock. There is a difference in definition of MSB and LSB of data, address, and parity pins between the TSOT0410G4 and some microprocessors, such as the Motorola MPC860. For example, the TSOT0410G4 provides Parity_1 and Parity_0. Parity_1 is the odd parity for the data bus MSB, and parity_0 is the odd parity for the data bus LSB. The MPC860 DP0 calculates across the data bus MSB, and DP1 across the data bus LSB. The microprocessor interface operates at the frequency of the microprocessor clock (PCLK) input in synchronous mode. The state of the MPMODE input signal determines whether bus transfers are synchronous or asynchronous with respect to PCLK. The TSOT0410G4 has separate 16-bit wide address and data buses. The microprocessor interface generates an external processor bus error if an internal data acknowledgement is not received in a predetermined period of time or on parity errors. Persistency alarm registers are used in conjunction with interrupt alarm registers to indicate whether alarms are persistent. Transfer Error Acknowledge (TEA_N) The TSOT0410G4 contains a bus time-out counter. When this counter saturates, a bus error is generated to the external processor through the transfer error acknowledge (TEA_N) signal. This feature must be considered with respect to the external processor's ability to generate its own internal bus time-out. TEA_N will be asserted if an internal data acknowledgement is not received within 32 PCLK periods of the start of the access. This interval is used since all valid internal accesses to the device will be completed in significantly less than 32 PCLK periods. TEA_N is also asserted if the calculated parity value does not match the parity generated by the external microprocessor on a data transfer. Interrupt Structure The interrupt structure of the TSOT0410G4 is designed to minimize the effort for software/firmware to isolate the interrupt source. The interrupt structure is comprised of different registers depending on the consolidation level. At the lowest level (source level) there are two registers. The first is an alarm register (AR). An alarm register is typically of the write 1 clear (W1C) type. The second is an interrupt mask (IM) register of the read/write (RW) type. An alarm register latches a raw status alarm. This latched alarm may contribute to an interrupt if its corresponding interrupt mask bit is disabled. Individual latched alarms are consolidated into an interrupt status register (ISR). If any of the latched alarms that are consolidated into a bit of an ISR are set and unmasked, the ISR bit is set. The ISR bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled. ISRs may be consolidated into higher-level ISR in a similar fashion until all alarms are consolidated into the chip-level ISR. The alarm register that causes an interrupt can be determined by traversing the tree of ISRs, starting at the chip-level ISR, until the source alarm is found. The interrupt requests can be selectively disabled on a per-function (per-bit) basis. The interrupt mask register serves this function. A bit position set to 1 indicates that the status flag in the corresponding bit position will not contribute to the generation of an interrupt when it is set (status itself is not affected by the interrupt mask). All interrupts are disabled on RST_N assertion.
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Data Sheet May 2003
Microprocessor Interface (continued)
Parity Bits There are two parity bits associated with the microprocessor interface. They are only active when the microprocessor interface is in synchronous mode (MPMODE = 1). PARITY_1 is the odd parity bit for the most significant 8 bits of the data bus (DATA_15 through DATA_8), and PARITY_0 is the odd parity bit for the least significant 8 bits of the data bus (DATA_7 through DATA_0). The parity bits may be ignored when the interface is operating in synchronous mode (MPMODE = 1); however, TEA_N must then be ignored on a write cycle. A TEA_N will never be asserted on a synchronous read cycle since the interface is presenting the parity on the output pins for the microprocessor interface to check. The parity bit pins may be left unconnected if not used. The parity bits are not used by the microprocessor interface when in asynchronous mode (MPMODE = 0), and can be unconnected. Clock Domains There are seven primary clock domains in the TSOT0410G4. Each has a separate clock source, related to the function of the domain. The microprocessor interface is a distinct clock domain and PCLK is its input clock. It contains the device-level registers. The clock domains are shown in Figure 9 on page 95. In the event that any domain loses its primary clock source, the microprocessor interface will not be able to access registers related to those regions until the clock is restored. The domain's clock is necessary internally to transfer data between that region of the device and the microprocessor interface. The receive line interface contains four clock domains, each clocked by R_CLK_[1--4], although they are all clocked by R_CLK_1 in STS-192 mode. The receive payload drop interface is a separate clock domain and is clocked by D_CLK. The separation between the receive domains is the receive drop aligner block. The transmit side of the device is an entire clock domain, with T_CLK as its input clock. The TSOT0410G device monitors RX_CLK_n, TX_CLK, and DRP_CLK to effectively detect loss of R_CLK_n, T_CLK, and D_CLK. Each clock is monitored by the same logic. P_CLK is divided by eight to produce a test signal that is less than 1/8th the clocks being monitored. This test signal is sampled using each of the monitored clocks, and then the sample is XORed with the test signal to generate a difference signal. This difference signal is then sampled by P_CLK at the end of each half cycle of the test clock. If the monitored clock is still active, the difference signal should be low by the end of the half cycle and the fail flag will stay low. If the monitored clock fails, the difference signal will be high during one of the half cycles of test signal, causing the fail alarm to strobe high. The status of RX_CLK_n, TX_CLK, and DRP_CLK are monitored using the clock loss alarm/PM clock detection register, address 0x7 (see Table 79 on page 113).
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
TLDCC_[1--4] TOHDAT_[1--4]_[1:0]
TOH_CLK_[1--4] TOW_CLK_[1--4] TSD_CLK_[1--4] TLD_CLK_[1--4]
TLCLOW_[1--4] TEXPOW_[1--4]
TSUSER_[1--4] TSDCC_[1--4]
TOHEN_[1--4] TOHFP_[1--4]
ADDRESS_[15:0]
PARITY_[1:0]
DATA_[15:0]
TFRM T_CLK TD_1_[3:0] TD_2_[3:0] TD_3_[3:0] TD_4_[3:0] T_CLKO_[1--4] X4 STS_MODE R_CLK_[1--4] SECTION TRACE BUFFER X4 RECEIVE STS-48 RECEIVE STS-192 TRANSPORT OVERHEAD LINE PROCESSOR INTERFACE PATH TRACE BUFFER RECEIVE PATH OVERHEAD PROCESSOR X4 STS PATH PROCESSING BLOCK X4 RECEIVE PAYLOAD DROP INTERFACE DFRM D_CLK DDATA_[16:1] DCTL_[1--4] RDDCC_[16:1] RDDCK_[1--4] JTAG INTERFACE X4 TRANSMIT STS-48 TRANSMIT STS-192 TRANSPORT OVERHEAD LINE PROCESSOR INTERFACE MICROPROCESSOR INTERFACE X4 TRANSMIT PAYLOAD ADD INTERFACE TADCC_[16:1] TADCK ADATA_[16:1] RST_N HIZ_N
RD_1_[3:0] RD_2_[3:0] RD_3_[3:0] RD_4_[3:0] RFRM[1--4]
RECEIVE DROP ALIGNER
RECEIVE POINTER PROCESSOR
R_CLKO_[1--4]
DRPBYP
TMS
TCK
PM_CLK
TEA_N
RW_N
INT_N
CS_N
DS_N
PCLK
TS_N
TA_N
REXPOW_[1--4]
RSUSER_[1--4]
RSDCC_[1--4]
RLCLOW_[1--4]
RLDCC_[1--4]
ROHDAT_[1--4]_[1:0]
ROHFP_[1--4]
x1 IN STS-192 MODE x4 IN STS-48 MODE
ROH_CLK_[1--4] ROW_CLK_[1--4] RSD_CLK_[1--4] RLD_CLK_[1--4]
TRST_N
TDO
TDI
MPMODE
5-7982(F).b
Note: See text for description of the timing domains.
Figure 9. TSOT0410G4 Timing Domains
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Persistency Registers
An alarm is persistent if it has been asserted continuously (i.e., the alarm has not been negated from the time it was asserted to the time it was read by software). An alarm is not persistent if it is negated one or more times from the point at which it was asserted to the point at which it was read by software. The persistency register monitors the state of an alarm point, and indicates to software whether the alarm is persistent. The following timing diagram indicates the operation of the persistency register relative to the raw status alarm, and its corresponding interrupt alarm register. It also describes the software interaction with respect to its attempt to clear the alarm, and its interpretation. At the rising edge of the raw alarm point, the corresponding interrupt alarm and persistency alarm register are set. The falling edge of the raw alarm causes the persistency alarm register to be reset (cleared). Any subsequent assertion of the raw alarm does not cause the persistency alarm register to be asserted. It remains reset until the interrupt alarm register is cleared (after the raw alarm is negated, and the interrupt alarm register is cleared). Once the interrupt alarm register is cleared, its corresponding persistency alarm register reset is released. The persistency register is now able to be set on the next assertion of the raw alarm point.
RAW ALARM
INTERRUPT ALARM REGISTER
PERSISTENCY REGISTER
5-8408(F)
Figure 10. Persistency Register Operation
Register Description
A summary of the available register addresses is provided in Table 71, beginning on page 97. Where two reset values exist, the first refers to STS-48 mode and the second refers to STS-192 mode.
Software Reset
The software reset (writing 0xEAEA to register 0xFF) resets most registers of the TSOT, with the exception of the device level registers: addresses 0x0 through 0x8. This is by design, since there is a design constraint in resetting the register that causes the reset. If necessary after a software reset, reconfigure 0x0 through 0x8. These registers do return to default values after a hardware reset. Note: The PLLs are not reset by a software reset. Although unlikely, should the need to reset the PLLs arise, a hardware reset should be asserted (RST_N).
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary Address (Hex) 0 1 2 3 4 5 6 7 8 9--FE FF 100--FFF 1000 1001 1100 1101 1102 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 111A 111B 111C 111D 111E 111F 1120 1121 1122 1123 1124 1125 1126 1127 Name Chip Level Interrupt Status Register Chip Level Interrupt Status Mask Register Chip ID Register Chip Vintage Register Scratch Pad Register Chip Level Maintenance Register Chip Status Register Clock Loss Alarm Register Clock Loss Alarm Mask Register Not Used Software Chip Reset Register Not Used LTE Interrupt Status Register LTE Interrupt Status Mask Register Section Trace (J0) Access Maintenance Register J0 Access Done Register J0 Access Message Start J0 Access Message Buffer, Word 1 J0 Access Message Buffer, Word 2 J0 Access Message Buffer, Word 3 J0 Access Message Buffer, Word 4 J0 Access Message Buffer, Word 5 J0 Access Message Buffer, Word 6 J0 Access Message Buffer, Word 7 J0 Access Message Buffer, Word 8 J0 Access Message Buffer, Word 9 J0 Access Message Buffer, Word 10 J0 Access Message Buffer, Word 11 J0 Access Message Buffer, Word 12 J0 Access Message Buffer, Word 13 J0 Access Message Buffer, Word 14 J0 Access Message Buffer, Word 15 J0 Access Message Buffer, Word 16 J0 Access Message Buffer, Word 17 J0 Access Message Buffer, Word 18 J0 Access Message Buffer, Word 19 J0 Access Message Buffer, Word 20 J0 Access Message Buffer, Word 21 J0 Access Message Buffer, Word 22 J0 Access Message Buffer, Word 23 J0 Access Message Buffer, Word 24 Bits 7:0 7:0 15:0 15:0 15:0 0:0 2:0 6:0 6:0 -- 15:0 -- 13:0 13:0 4:0 0 0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Reset 0x0 0x0 0x1515 0x1 0x0 0x0 -- 0x0 0x0 -- 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 97
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 1128 1129 112A 112B 112C 112D 112E 112F 1130-- 12FF 1300 1301 1302 1303 1304 1305 1306 1307 1308-- 1309 1310 1311 1312 1313 1314 1315 1316 1317-- 1319 1320 1321 1322 1323 1324 1325 1326 98 Name J0 Access Message Buffer, Word 25 J0 Access Message Buffer, Word 26 J0 Access Message Buffer, Word 27 J0 Access Message Buffer, Word 28 J0 Access Message Buffer, Word 29 J0 Access Message Buffer, Word 30 J0 Access Message Buffer, Word 31 J0 Access Message Buffer, Word 32 Not Used Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-3) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-4) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-5) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-6) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-7) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-8) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-9) Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-10) Not Used Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-3) Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-4) Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-5) Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-6) Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-7) Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-8) Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-9) Not Used Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-4) Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-5) Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-6) Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-7) Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-8) Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-9) Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-10) Bits 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 -- 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 -- 15:0 15:0 15:0 15:0 15:0 15:0 15:0 -- 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x8/0x8 0x8/0x8 0x8/0x8 0x3E/0xD 0x271/0x82 0x1450/ 0x514 0x8015/ 0x2904 0x80AA/ 0x8029 -- 0x12D2/ 0x4BFD 0x35E/ 0xDD7 0x51/0x166 0x3E/0x33 0x3E/0x33 0x33/0x33 0x28/0x28 -- 0x3BD/ 0xE96 0x72/0x1A7 0x5B/0x4D 0x5B/0x4D 0x4D/0x4D 0x3F/0x3F 0x34/0x33
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 1327-- 13FF 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 140A 140B 140C 140D 140E 140F 1410 1411-- 14FF 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 150A 150B 150C 150D 150E 150F 1510 1511-- 15FF 1600 Not Used LTE Receive Channel 1 Provisioning Register LTE Receive Channel 1 Maintenance Register LTE Receive Channel 1 Loss of Signal (LOS) Threshold LTE Receive Channel 1 K Byte Status Register LTE Receive Channel 1 S1 Byte Status Register LTE Receive Channel 1 Service-Affecting Interrupt Alarm Register LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask Register LTE Receive Channel 1 Service-Affecting Persistency Alarm Register LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm Register LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm Mask Register LTE Receive Channel 1 NSA Persistency Alarm Register LTE Receive Channel 1 Performance Monitoring Register LTE Receive Channel 1 REI-L Performance Monitoring Register (L) LTE Receive Channel 1 REI-L Performance Monitoring Register (U) LTE Receive Channel 1 CV-L Performance Monitoring Register (L) LTE Receive Channel 1 CV-L Performance Monitoring Register (U) LTE Receive Channel 1 CV-S Performance Monitoring Register Not Used LTE Receive Channel 2 Provisioning Register LTE Receive Channel 2 Maintenance Register LTE Receive Channel 2 Loss of Signal (LOS) Threshold LTE Receive Channel 2 K Byte Status Register LTE Receive Channel 2 S1 Byte Status Register LTE Receive Channel 2 Service-Affecting Interrupt Alarm Register LTE Receive Channel 2 Service-Affecting Interrupt Alarm Mask Register LTE Receive Channel 2 Service-Affecting Persistency Alarm Register LTE Receive Channel 2 Nonservice-Affecting Interrupt Alarm Register LTE Receive Channel 2 Nonservice-Affecting Interrupt Alarm Mask Register LTE Receive Channel 2 NSA Persistency Alarm Register LTE Receive Channel 2 Performance Monitoring Register LTE Receive Channel 2 REI-L Performance Monitoring Register (L) LTE Receive Channel 2 REI-L Performance Monitoring Register (U) LTE Receive Channel 2 CV-L Performance Monitoring Register (L) LTE Receive Channel 2 CV-L Performance Monitoring Register (U) LTE Receive Channel 2 CV-S Performance Monitoring Register Not Used LTE Receive Channel 3 Provisioning Register Name Bits -- 6:0 6:0 9:0 15:0 7:0 4:0 4:0 2:0 10:0 10:0 5:0 4:0 15:0 4:0 15:0 7:0 15:0 -- 6:0 6:0 9:0 15:0 7:0 4:0 4:0 2:0 10:0 10:0 5:0 4:0 15:0 4:0 15:0 7:0 15:0 -- 6:0 Reset -- 0x2 0x20 0x86 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x2 0x20 0x86 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x2 99
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 1601 1602 1603 1604 1605 1606 1607 1608 1609 160A 160B 160C 160D 160E 160F 1610 1611-- 16FF 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 170A 170B 170C 170D 170E 170F 1710 1711-- 1AFF 1B00 1B01 1B02 1B03 100 Name LTE Receive Channel 3 Maintenance Register LTE Receive Channel 3 Loss of Signal (LOS) Threshold LTE Receive Channel 3 K Byte Status Register LTE Receive Channel 3 S1 Byte Status Register LTE Receive Channel 3 Service-Affecting Interrupt Alarm Register LTE Receive Channel 3 Service-Affecting Interrupt Alarm Mask Register LTE Receive Channel 3 Service-Affecting Persistency Alarm Register LTE Receive Channel 3 Nonservice-Affecting Interrupt Alarm Register LTE Receive Channel 3 Nonservice-Affecting Interrupt Alarm Mask Register LTE Receive Channel 3 NSA Persistency Alarm Register LTE Receive Channel 3 Performance Monitoring Register LTE Receive Channel 3 REI-L Performance Monitoring Register (L) LTE Receive Channel 3 REI-L Performance Monitoring Register (U) LTE Receive Channel 3 CV-L Performance Monitoring Register (L) LTE Receive Channel 3 CV-L Performance Monitoring Register (U) LTE Receive Channel 3 CV-S Performance Monitoring Register Not Used LTE Receive Channel 4 Provisioning Register LTE Receive Channel 4 Maintenance Register LTE Receive Channel 4 Loss of Signal (LOS) Threshold LTE Receive Channel 4 K Byte Status Register LTE Receive Channel 4 S1 Byte Status Register LTE Receive Channel 4 Service-Affecting Interrupt Alarm Register LTE Receive Channel 4 Service-Affecting Interrupt Alarm Mask Register LTE Receive Channel 4 Service-Affecting Persistency Alarm Register LTE Receive Channel 4 Nonservice-Affecting Interrupt Alarm Register LTE Receive Channel 4 Nonservice-Affecting Interrupt Alarm Mask Register LTE Receive Channel 4 NSA Persistency Alarm Register LTE Receive Channel 4 Performance Monitoring Register LTE Receive Channel 4 REI-L Performance Monitoring Register (L) LTE Receive Channel 4 REI-L Performance Monitoring Register (U) LTE Receive Channel 4 CV-L Performance Monitoring Register (L) LTE Receive Channel 4 CV-L Performance Monitoring Register (U) LTE Receive Channel 4 CV-S Performance Monitoring Register Not Used LTE Transmit--Frame Pulse Offset Count LTE Transmit--B1 Corrupt Frame Count LTE Transmit--B2 Corrupt Frame Count LTE Transmit--M1 Corrupt Frame Count Bits 6:0 9:0 15:0 7:0 4:0 4:0 2:0 10:0 10:0 5:0 4:0 15:0 4:0 15:0 7:0 15:0 -- 6:0 6:0 9:0 15:0 7:0 4:0 4:0 2:0 10:0 10:0 5:0 4:0 15:0 4:0 15:0 7:0 15:0 -- 13:0 12:0 12:0 12:0 Reset 0x20 0x86 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x2 0x20 0x86 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0
Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 1B04 1B05 1B06 1B07-- 1BFF 1C00 1C01 1C02 1C03 1C04 1C05 1C06 1C07 1C08 1C09 1C0A 1C0B 1C0C 1C0D 1C0E-- 1CFF 1D00 1D01 1D02 1D03 1D04 1D05 1D06 1D07 1D08 1D09 1D0A 1D0B 1D0C 1D0D 1D0E-- 1DFF 1E00 1E01 1E02 1E03 Name LTE Transmit--TFRM S1 Byte LTE Transmit--Interrupt Alarm Register LTE Transmit--Interrupt Alarm Mask Register Not Used LTE Transmit Channel 1 Provisioning Register LTE Transmit Channel 1 Maintenance Register LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2 LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3 LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4 LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2 LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3 LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4 LTE Transmit Channel 1 K1K2 Byte Insert Values LTE Transmit Channel 1 S1 Byte Insert Value LTE Transmit Channel 1 Interrupt Alarm Register LTE Transmit Channel 1 Interrupt Alarm Mask Register Not Used LTE Transmit Channel 2 Provisioning Register LTE Transmit Channel 2 Maintenance Register LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #1 LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #2 LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #3 LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #4 LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #1 LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #2 LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #3 LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #4 LTE Transmit Channel 2 K1K2 Byte Insert Values LTE Transmit Channel 2 S1 Byte Insert Value LTE Transmit Channel 2 Interrupt Alarm Register LTE Transmit Channel 2 Interrupt Alarm Mask Register Not Used LTE Transmit Channel 3 Provisioning Register LTE Transmit Channel 3 Maintenance Register LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #1 LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #2 Bits 7:0 2:0 2:0 -- 5:0 5:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 15:0 7:0 1:0 1:0 -- 5:0 5:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 15:0 7:0 1:0 1:0 -- 5:0 5:0 11:0 11:0 Reset 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 101
Agere Systems Inc.
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 1E04 1E05 1E06 1E07 1E08 1E09 1E0A 1E0B 1E0C 1E0D 1E0E-- 1EFF 1F00 1F01 1F02 1F03 1F04 1F05 1F06 1F07 1F08 1F09 1F0A 1F0B 1F0C 1F0D 1F0E-- 1FFF 2000 2001 2002 2003 2004-- 23FF 2400 2401 2402 2403 2404 2405 2406 102 Name LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #3 LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #4 LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #1 LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #2 LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #3 LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #4 LTE Transmit Channel 3 K1K2 Byte Insert Values LTE Transmit Channel 3 S1 Byte Insert Value LTE Transmit Channel 3 Interrupt Alarm Register LTE Transmit Channel 3 Interrupt Alarm Mask Register Not Used LTE Transmit Channel 4 Provisioning Register LTE Transmit Channel 4 Maintenance Register LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #1 LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #2 LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #3 LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #4 LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #1 LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #2 LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #3 LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #4 LTE Transmit Channel 4 K1K2 Byte Insert Values LTE Transmit Channel 4 S1 Byte Insert Value LTE Transmit Channel 4 Interrupt Alarm Register LTE Transmit Channel 4 Interrupt Alarm Mask Register Not Used EQPT Interrupt Status Register EQPT Interrupt Mask Register Receive Drop Common Service-Affecting Alarm Register Receive Drop Common Service-Affecting Alarm Mask Register Not Used Receive Drop STS-48 Channel Provisioning Register 1 J0 Trace--STS-12 Channel 1 J0 Trace--STS-12 Channel 2 J0 Trace--STS-12 Channel 3 J0 Trace--STS-12 Channel 4 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 1 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 1 Bits 11:0 11:0 11:0 11:0 11:0 11:0 15:0 7:0 1:0 1:0 -- 5:0 5:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 15:0 7:0 1:0 1:0 -- 12:0 12:0 0 0 -- 1:0 7:0 7:0 7:0 7:0 4:0 4:0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 -- 0x0 0x1 0x2 0x3 0x4 0x0 0x0
Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 2407-- 24FF 2500 2501 2502 2503 2504 2505 2506 2507-- 25FF 2600 2601 2602 2603 2604 2605 2606 2607-- 26FF 2700 2701 2702 2703 2704 2705 2706 2707-- 27FF 2C00 2C01 2C02 2C03 2C04 2C05 2C06 2C07 2C08 2C09 2C0A Not Used Receive Drop STS-48 Channel Provisioning Register 2 J0 Trace--STS-12 Channel 5 J0 Trace--STS-12 Channel 6 J0 Trace--STS-12 Channel 7 J0 Trace--STS-12 Channel 8 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 2 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 2 Not Used Receive Drop STS-48 Channel Provisioning Register 3 J0 Trace--STS-12 Channel 9 J0 Trace--STS-12 Channel 10 J0 Trace--STS-12 Channel 11 J0 Trace--STS-12 Channel 12 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 3 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 3 Not Used Receive Drop STS-48 Channel Provisioning Register 4 J0 Trace--STS-12 Channel 13 J0 Trace--STS-12 Channel 14 J0 Trace--STS-12 Channel 15 J0 Trace--STS-12 Channel 16 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 4 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 4 Not Used Transmit Add STS-48 Channel Provisioning Register #1 J0 Status Register--1, STS-48 #1 J0 Status Register--2, STS-48 #1 J0 Status Register--3, STS-48 #1 J0 Status Register--4, STS-48 #1 AIS Insert Status Register, STS-12 Channel #1, STS-48 #1 AIS Insert Status Register, STS-12 Channel #2, STS-48 #1 AIS Insert Status Register, STS-12 Channel #3, STS-48 #1 AIS Insert Status Register, STS-12 Channel #4, STS-48 #1 Transmit Add STS-48 Channel Alarm Register #1 Transmit Add STS-48 Channel Alarm Mask Register #1 Name Bits -- 1:0 7:0 7:0 7:0 7:0 4:0 4:0 -- 1:0 7:0 7:0 7:0 7:0 4:0 4:0 -- 1:0 7:0 7:0 7:0 7:0 4:0 4:0 -- 1:0 7:0 7:0 7:0 7:0 11:0 11:0 11:0 11:0 14:0 14:0 Reset -- 0x0 0x5 0x6 0x7 0x8 0x0 0x0 -- 0x0 0x9 0x10 0x11 0x12 0x0 0x0 -- 0x0 0x13 0x14 0x15 0x16 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Agere Systems Inc.
103
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 2C0B-- 2CFF 2D00 2D01 2D02 2D03 2D04 2D05 2D06 2D07 2D08 2D09 2D0A 2D0B-- 2DFF 2E00 2E01 2E02 2E03 2E04 2E05 2E06 2E07 2E08 2E09 2E0A 2E0B-- 2EFF 2F00 2F01 2F02 2F03 2F04 2F05 2F06 2F07 2F08 2F09 2F0A 2F0B-- 2FFF 104 Not Used Transmit Add STS-48 Channel Provisioning Register #2 J0 Status Register--1, STS-48 #2 J0 Status Register--2, STS-48 #2 J0 Status Register--3, STS-48 #2 J0 Status Register--4, STS-48 #2 AIS Insert Status Register, STS-12 Channel #1, STS-48 #2 AIS Insert Status Register, STS-12 Channel #2, STS-48 #2 AIS Insert Status Register, STS-12 Channel #3, STS-48 #2 AIS Insert Status Register, STS-12 Channel #4, STS-48 #2 Transmit Add STS-48 Channel Alarm Register #2 Transmit Add STS-48 Channel Alarm Mask Register #2 Not Used Transmit Add STS-48 Channel Provisioning Register #3 J0 Status Register--1, STS-48 #3 J0 Status Register--2, STS-48 #3 J0 Status Register--3, STS-48 #3 J0 Status Register--4, STS-48 #3 AIS Insert Status Register, STS-12 Channel #1, STS-48 #3 AIS Insert Status Register, STS-12 Channel #2, STS-48 #3 AIS Insert Status Register, STS-12 Channel #3, STS-48 #3 AIS Insert Status Register, STS-12 Channel #4, STS-48 #3 Transmit Add STS-48 Channel Alarm Register #3 Transmit Add STS-48 Channel Alarm Mask Register #3 Not Used Transmit Add STS-48 Channel Provisioning Register #4 J0 Status Register--1, STS-48 #4 J0 Status Register--2, STS-48 #4 J0 Status Register--3, STS-48 #4 J0 Status Register--4, STS-48 #4 AIS Insert Status Register, STS-12 Channel #1, STS-48 #4 AIS Insert Status Register, STS-12 Channel #2, STS-48 #4 AIS Insert Status Register, STS-12 Channel #3, STS-48 #4 AIS Insert Status Register, STS-12 Channel #4, STS-48 #4 Transmit Add STS-48 Channel Alarm Register #4 Transmit Add STS-48 Channel Alarm Mask Register #4 Not Used Name Bits -- 1:0 7:0 7:0 7:0 7:0 11:0 11:0 11:0 11:0 14:0 14:0 -- 1:0 7:0 7:0 7:0 7:0 11:0 11:0 11:0 11:0 14:0 14:0 -- 1:0 7:0 7:0 7:0 7:0 11:0 11:0 11:0 11:0 14:0 14:0 -- Reset -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 --
Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 3000 3001 3002 3003 3004 3005 3006-- 300F 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 ... 3028 ... 30C0 ... 30C8 3100 ... 31C8 ... 3F00 ... 3FC8 3FC9-- 3FFF 4000 4001 4002 Name STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to STS-1 #12 STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to STS-1 #12 STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to STS-1 #12 STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to STS-1 #12 Not Used STS-1 #1 Path Overhead Provisioning STS-1 #1 Path Overhead Maintenance STS-1 #1 Path Overhead Status STS-1 #1 Alarm Interrupt Status STS-1 #1 Alarm Interrupt Status Mask STS-1 #1 Alarm Persistency STS-1 #1 PM Last Second Indicators STS-1 #1 Last Second CV-P Count STS-1 #1 Last Second REI-P Count Not Used STS-1 #2 Path Overhead Provisioning ... STS-1 #2 Last Second REI-P Count ... STS-1 #12 Path Overhead Provisioning ... STS-1 #12 Last Second REI-P Count STS-12 Pointer Processor Provisioning, STS-1 #13 to STS-1 #24 ... STS-1 #24 Last Second REI-P Count ... STS-12 Pointer Processor Provisioning, STS-1 #181 to STS-1 #192 ... STS-1 #192 Last Second REI-P Count Not Used Path Overhead (POH) Interrupt Status Register Path Overhead (POH) Interrupt Status Mask Register Path STS-1 Signal Fail Detect Threshold, Window Size Select 0 Bits 5:0 11:0 10:0 10:0 10:0 10:0 -- 15:0 3:0 10:0 6:0 6:0 4:0 6:0 15:0 15:0 -- 15:0 15:0 15:0 15:0 5:0 15:0 5:0 15:0 -- 15:0 15:0 15:0 Reset 0x11 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x11 0x0 0x11 0x0 -- 0x0 0x0 0x40CF 105
Agere Systems Inc.
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 4003 4004 4005 4006 4007 4008 4009 400A 400B 400C 400D 400E 400F 4010 4011 4012 4013 4014 4015 4016-- 46FF 4100 4101 4102 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 106 Name Path STS-1 Signal Fail Clear Threshold, Window Size Select 0 Path STS-1 Signal Fail Detect Threshold, Window Size Select 1 Path STS-1 Signal Fail Clear Threshold, Window Size Select 1 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 2 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 2 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 3 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 3 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 4 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 4 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 5 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 5 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 6 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 6 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 7 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 7 Path Signal Fail Window Size Path Signal Fail Window Size Path Signal Fail Window Size Path Signal Fail Window Size Not Used Path Trace Access Control Path Trace Access Complete Status Path Trace Access Start Path Trace Buffer Word #1 Path Trace Buffer Word #2 Path Trace Buffer Word #3 Path Trace Buffer Word #4 Path Trace Buffer Word #5 Path Trace Buffer Word #6 Path Trace Buffer Word #7 Path Trace Buffer Word #8 Path Trace Buffer Word #9 Path Trace Buffer Word #10 Path Trace Buffer Word #11 Path Trace Buffer Word #12 Path Trace Buffer Word #13 Path Trace Buffer Word #14 Path Trace Buffer Word #15 Path Trace Buffer Word #16 Path Trace Buffer Word #17 Bits 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 -- 3:0 0 0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 Reset 0x8113 0x80DE 0xC115 0x4233 0x830B 0x82B2 0xC31B 0x43A3 0x85D8 0x855E 0xC618 0x451D 0x8B08 0x8A62 0xCBFC 0xA 0x64 0x3E8 0x2710 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 4121 4122 4123 4124 4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F 4130-- 43FF 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 440A 440B 440C 440D 440E 440F 4410 4411 4412 4413 4414 4415-- 44FF Path Trace Buffer Word #18 Path Trace Buffer Word #19 Path Trace Buffer Word #20 Path Trace Buffer Word #21 Path Trace Buffer Word #22 Path Trace Buffer Word #23 Path Trace Buffer Word #24 Path Trace Buffer Word #25 Path Trace Buffer Word #26 Path Trace Buffer Word #27 Path Trace Buffer Word #28 Path Trace Buffer Word #29 Path Trace Buffer Word #30 Path Trace Buffer Word #31 Path Trace Buffer Word #32 Not Used STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (STS-48 #1) STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #1) STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #1) STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #1) STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #1) STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #1) STS-48 #1 Channel Path Trace Control S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #1) S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #1) S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #1) S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #1) S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #1) S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #1) S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #1) S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #1) Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #1) Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #1) Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #1) Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #1) STS-48 Channel 1, Path Interrupt Status STS-48 Channel 1, Path Interrupt Status Mask Not Used Name Bits 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 -- 15:0 15:0 15:0 15:0 15:0 15:0 9:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 -- Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 --
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 450A 450B 450C 450D 450E 450F 4510 4511 4512 4513 4514 4515-- 45FF 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 460A 460B 460C 460D 460E 460F 4610 4611 108 Name STS-1 Channel Interrupt Status, STS-1 #49 to STS-1 #64 (STS-48 #2) STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #2) STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #2) STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #2) STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #2) STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #2) STS-48 #2 Channel Path Trace Control S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #2) S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #2) S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #2) S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #2) S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #2) S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #2) S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #2) S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #2) Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #2) Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #2) Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #2) Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #2) STS-48 Channel 2, Path Interrupt Status STS-48 Channel 2, Path Interrupt Status Mask Not Used STS-1 Channel Interrupt Status, STS-1 #97 to STS-1 #112 (STS-48 #3) STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #3) STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #3) STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #3) STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #3) STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #3) STS-48 #3 Channel Path Trace Control S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #3) S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #3) S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #3) S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #3) S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #3) S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #3) S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #3) S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #3) Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #3) Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #3) Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #3) Bits 15:0 15:0 15:0 15:0 15:0 15:0 9:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 -- 15:0 15:0 15:0 15:0 15:0 15:0 9:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 71. Register Summary (continued) Address (Hex) 4612 4613 4614 4615-- 46FF 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 470A 470B 470C 470D 470E 470F 4710 4711 4712 4713 4714 Name Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #3) STS-48 Channel 3, Path Interrupt Status STS-48 Channel 3, Path Interrupt Status Mask Not Used STS-1 Channel Interrupt Status, STS-1 #145 to STS-1 #160 (STS-48 #4) STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #4) STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #4) STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #4) STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #4) STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #4) STS-48 #4 Channel Path Trace Control S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #4) S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #4) S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #4) S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #4) S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #4) S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #4) S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #4) S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #4) Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #4) Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #4) Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #4) Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #4) STS-48 Channel 4, Path Interrupt Status STS-48 Channel 4, Path Interrupt Status Mask Bits 11:0 11:0 11:0 -- 15:0 15:0 15:0 15:0 15:0 15:0 9:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 Reset 0x0 0x0 0x0 -- 0x0 0x0 0x0 0x0 0x0 0x0 0x200 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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Microprocessor Interface (continued)
Device-Level Registers
This section gives a brief description of each register bit and its functionality. The abbreviations after each register indicate if the register is read only (RO), write one clear (W1C), read/write (R/W), or write only (WO). W1C mode will clear bits to which a 1 is written. Bits written to 0 are not cleared. Table 72. Interrupt Status (RO) Address (Hex) 0 Bit 15:8 7 Name -- CHIP_EQPT_NSA Description Unused. EQPT Nonservice-Affecting Alarms. Source--register 0x2000, bits 4--7, 9--12. See Table 150 on page 134. EQPT Service-Affecting Alarms. Source--register 0x2000, bits 0--3, 8. See Table 150 on page 134. POH STS-48 Channel Alarms. Source--register 0x4000, bits 12--15. See Table 187 on page 149. POH STS-1 Channel Alarms. Source--register 0x4000, bits 0--11. See Table 187 on page 149. LTE Nonservice-Affecting Alarms. Source--register 0x1000, bits 4--7, 9--13. See Table 82 on page 115. LTE Service-Affecting Alarms. Source--register 0x1000, bits 0--3, 8. See Table 82 on page 115. PMCLK Positive Edge Detected. Source--register 0x7, bit 6. See Table 79 on page 113. Clock Loss Alarms. Source--register 0x7, bits 0--5. See Table 79 on page 113. Reset 0 0
6 5 4 3 2 1 0
CHIP_EQPT_SA CHIP_POH_STS48 CHIP_POH_STS1 CHIP_LTE_NSA CHIP_LTE_SA CHIP_PM_CLK CHIP_CLK_LOSS
0 0 0 0 0 0 0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 73. Interrupt Status Mask (R/W) Address (Hex) 1 Bit 15:8 7 Name -- CHIP_EQPT_NSA_M Description Reset 0 0
6
5
4
3
2
1
0
Unused. Program to zero. EQPT Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_EQPT_SA_M EQPT Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_POH_STS48_M POH STS-48 Channel Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_POH_STS1_M POH STS-1 Channel Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_LTE_NSA_M LTE Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_LTE_SA_M LTE Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_PM_CLK_M PMCLK Positive Edge Detected Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHIP_CLK_LOSS_M Clock Loss Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
0
0
0
0
0
Table 74. Chip ID (RO) Address (Hex) 2 Bit 15:0 Name CHIP_ID Description Reset
Chip Identification Code. Register always reads 0x1515 as 0x1515.
Table 75. Chip Vintage (RO) Address (Hex) 3 Bit 15:0 Name CHIP_VINTAGE Description Chip Vintage Code. Register always reads as 0x0005. Reset 0x1
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Microprocessor Interface (continued)
Table 76. Scratch Pad, Clock Loss Alarm (R/W) Address (Hex) 4 Bit 15:0 Name SCRATCH_PAD Description Scratch Pad Register. Does not impact device operation. Reset 0
Table 77. Chip-Level Maintenance (R/W) Address (Hex) 5 Bit 15:1 0 Name -- FRC_PAR_ERR Description Unused. Program to zero. Force Parity Error Alarms (all data paths and memories). 1 = Forces an internal parity error alarm. 0 = Normal operation. Reset 0 0
Table 78. Chip Status (RO) Address (Hex) 6 Bit 15:3 2 Name -- DRPBYP Description Unused. State of DRPBYP Pin. 1 = Pointer generator is bypassed. 0 = Pointer generator is enabled. State of STS_MODE Pin. 1 = STS-48. 0 = STS-192. Chip Interrupt Activity Status (i.e., inverted INT_N). 1 = Interrupt pin is asserted. 0 = No interrupt. Reset 0 Pin State Pin State 0
1
STS_MODE
0
CHIP_INT
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 79. Clock Loss Alarm/PM Clock Detection (W1C) Address (Hex) 7 Bit 15:7 6 Name -- PM_CLK Description Unused. May write ones on clear (W1C) if desired. PMCLK Strobe Positive Edge Detected (sampled by PCLK). 1 = PMCLK detected. 0 = PMCLK not detected. Loss of Clock--D_CLK. 1 = Loss of clock. 0 = D_CLK detected. Loss of Clock--T_CLK. 1 = Loss of clock. 0 = T_CLK detected. Loss of Clock--R_CLK_4. 1 = Loss of clock. 0 = R_CLK_4 detected. Loss of Clock--R_CLK_3. 1 = Loss of clock. 0 = R_CLK_3 detected. Loss of Clock--R_CLK_2. 1 = Loss of clock. 0 = R_CLK_2 detected. Loss of Clock--R_CLK_1. 1 = Loss of clock. 0 = R_CLK_1 detected. Reset 0 0
5
D_CLK_FAIL
0
4
T_CLK_FAIL
0
3
R_CLK_4_FAIL
0
2
R_CLK_3_FAIL
0
1
R_CLK_2_FAIL
0
0
R_CLK_1_FAIL
0
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Microprocessor Interface (continued)
Table 80. Clock Loss Alarm/PM Clock Detection Mask (R/W) Address (Hex) 8 Bit 15:7 6 Name -- PM_CLK_M Description Unused. Program to zero. PMCLK Strobe Positive Edge Detected (sampled by PCLK) Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Clock--D_CLK Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Clock--T_CLK Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Clock--R_CLK_4 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Clock--R_CLK_3 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Clock--R_CLK_2 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Clock--R_CLK_1 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
5
D_CLK_FAIL_M
0
4
T_CLK_FAIL_M
0
3
R_CLK_4_FAIL_M
0
2
R_CLK_3_FAIL_M
0
1
R_CLK_2_FAIL_M
0
0
R_CLK_1_FAIL_M
0
Table 81. Software Chip Reset (WO) Address (Hex) FF Bit 15:0 Name CHIP_SW_RESET Description Force Hardware Reset to Entire Chip. Write 0xEAEA to initiate reset. Register always reads as 0x0000. See the Software Reset section on page 96 for details. Reset 0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Line Terminating Equipment (LTE) Registers
The LTE registers are divided into six functional groups as follows:
s
LTE Common Registers: contains the interrupt status register and the associated mask register that consolidates the alarms for the LTE. LTE J0 Access Registers: used to read and provision J0 messages for both the receive and transmit direction. Signal Degrade/Signal Fail Registers: allows the configuration of the detection time, error limits, and clear error limit for signal fail and signal degrade detection. These registers are common to all four receive STS-48 channels. LTE Receive Channel 1, 2, 3, and 4 Registers: provisioning, maintenance, alarm, and status registers for the individual receive STS-48 channels. In STS-192 mode, only the first channel registers are used (except for the receive overhead data (ROHDAT) memory parity error alarm, which is valid in all four channels). LTE Transmit Common Registers: provisioning, maintenance, alarm, and status registers that are shared between all four transmit STS-48 channels. LTE Transmit Channel 1, 2, 3, and 4 Registers: provisioning, maintenance, alarm, and status registers for the individual transmit STS-48 channels. In STS-192 mode, only the first channel registers are used (except for the transmit overhead data (ROHDAT) memory parity error alarm, which is valid in all four channels).
s s
s
s
s
LTE Common Registers Table 82. LTE Interrupt Status (RO) Address (Hex) 1000 Bit 15:14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Agere Systems Inc. Name -- LTE_TX_4_NSA LTE_TX_3_NSA LTE_TX_2_NSA LTE_TX_1_NSA LTE_TX_COMMON_NSA LTE_TX_COMMON_SA LTE_RX_4_NSA LTE_RX_3_NSA LTE_RX_2_NSA LTE_RX_1_NSA LTE_RX_4_SA LTE_RX_3_SA LTE_RX_2_SA LTE_RX_1_SA Unused. Transmit Channel 4 Nonservice-Affecting Alarms. Transmit Channel 3 Nonservice-Affecting Alarms. Transmit Channel 2 Nonservice-Affecting Alarms. Transmit Channel 1 Nonservice-Affecting Alarms. Transmit Nonservice-Affecting Alarms. Transmit Service-Affecting Alarms. Receive Channel 4 Nonservice-Affecting Alarms. Receive Channel 3 Nonservice-Affecting Alarms. Receive Channel 2 Nonservice-Affecting Alarms. Receive Channel 1 Nonservice-Affecting Alarms. Receive Channel 4 Service-Affecting Alarms. Receive Channel 3 Service-Affecting Alarms. Receive Channel 2 Service-Affecting Alarms. Receive Channel 1 Service-Affecting Alarms. Description Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 115
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Data Sheet May 2003
Microprocessor Interface (continued)
Table 83. LTE Interrupt Status Mask (R/W) Address (Hex) 1001 Bit 15:14 13 Name -- LTE_TX_4_NSA_M Description Reset 0 0
12
11
10
9
8
7
6
5
4
Unused. Program to zero. Transmit Channel 4 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_TX_3_NSA_M Transmit Channel 3 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_TX_2_NSA_M Transmit Channel 2 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_TX_1_NSA_M Transmit Channel 1 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_TX_COMMON_NSA_M Transmit Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_TX_COMMON_SA_M Transmit Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_RX_4_NSA_M Receive Channel 4 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_RX_3_NSA_M Receive Channel 3 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_RX_2_NSA_M Receive Channel 2 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. LTE_RX_1_NSA_M Receive Channel 1 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
0
0
0
0
0
0
0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 83. LTE Interrupt Status Mask (R/W) (continued) Address (Hex) 1001 Bit 3 Name LTE_RX_4_SA_M Description Receive Channel 4 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Receive Channel 3 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Receive Channel 2 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Receive Channel 1 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
2
LTE_RX_3_SA_M
0
1
LTE_RX_2_SA_M
0
0
LTE_RX_1_SA_M
0
LTE J0 Access Registers The J0 access registers are used to read and provision the section trace messages for both the receive and transmit direction. The first step in reading or provisioning a message involves configuring the section trace access maintenance register for the type of access that is to be performed. If a message write operation is being performed, the message buffer should then be programmed with the desired section trace message to be written to the selected J0 memory. To start the transfer, write a 0x0001 to the J0 access message start register at which point the transfer occurs on a non-real-time basis. The J0 access done flag indicates the completion of the message transfer. If a read operation was specified, the J0 access message buffer now contains the contents of the selected message. Note: To insert J0 into the transmit stream, 0x0020 must be written register 0x1C01 (the enable insertion of provisioned J0 message register). See Table 137 on page 131 for detailed register information. Table 84. Section Trace (J0) Access Maintenance (R/W) Address (Hex) 1100 Bit 15:5 4:3 2 Name -- J_ACCESS_CH_NUM J_ACCESS_DIR Description Unused. Program to zero. J0 Access Channel Number (0 to 3). J0 Access Direction. 1 = Transmit. 0 = Receive. Received Message Type. 1 = Provisioned. 0 = Validated. Message Read/Write. 1 = Write. 0 = Read. Reset 0 0 0
1
J_ACCESS_MSG_TYPE
0
0
J_ACCESS_RW
0
Note: When the J_Access_Dir bit is set to 1 (transmit), the J_Access_Msg_Type bit is unused.
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Microprocessor Interface (continued)
Table 85. J0 Access Done (W1C) Address (Hex) 1101 Bit 15:1 0 Name -- J_ACCESS_DONE_FLAG Description Unused. May write ones on clear (W1C) if desired. Access Done Flag. Reset 0 0
Note: The J0 access done flag is a write 1 clear (W1C) register, but does not generate an interrupt.
Table 86. J0 Access Message Start (WO) Address (Hex) 1102 Bit 15:1 0 Name Description Reset 0 0
-- Unused. Program to zero. LTE_J_ACCESS_MSG_START Access Started Flag.
To start a J0 message transfer, write the value 0x0001 to this register. A read of this register is undefined and should not be performed. Table 87. J0 Access Message Buffers 1--32 (R/W) Address (Hex) 1110--112F Bit 15:0 Name LTE_J_ACCESS_BUF_n Description J0 Message Bytes. Reset 0
The J0 access message buffer is organized as thirty-two 16-bit registers, which allows storage of 1 section trace message. The beginning of the message should be stored in the lower byte of the first register (i.e., J0 access message buffer word 1, address 1110, bits 7:0). For SDH messages, only the first eight registers contain the actual message (i.e., 16 bytes); the other registers are undefined. During a read operation, the contents of the J0 access message buffer is overwritten with the contents of the desired message.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Signal Degrade/Signal Fail Registers The SD/SF registers listed below are shared between all four receive STS-48 channels. Selection of the bit rate for each channel is done using the corresponding LTE receive channel [1--4] maintenance register. The reset value for the SD/SF registers depends on the state of the STS_MODE pin. In the tables below, the first value in the reset field indicates the reset value of the register when the device is operating in STS-48 mode, and the second value is used in STS-192 mode. Both values are given in decimal format. Table 88. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-3) (R/W) Address (Hex) 1300 Bit 15 14:0 Name SD_SF_DETECT_UNIT_3 SD_SF_DETECT_TIME_3 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10 .
-3
Reset 0/0 8/8
Table 89. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-4) (R/W) Address (Hex) 1301 Bit 15 14:0 Name SD_SF_DETECT_UNIT_4 SD_SF_DETECT_TIME_4 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10 .
-4
Reset 0/0 8/8
Table 90. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-5) (R/W) Address (Hex) 1302 Bit 15 14:0 Name SD_SF_DETECT_UNIT_5 SD_SF_DETECT_TIME_5 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10-5. Reset 0/0 8/8
Table 91. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-6) (R/W) Address (Hex) 1303 Bit 15 14:0 Name SD_SF_DETECT_UNIT_6 SD_SF_DETECT_TIME_6 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10-6. Reset 0/0 62/13
Table 92. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-7) (R/W) Address (Hex) 1304 Bit 15 14:0 Name SD_SF_DETECT_UNIT_7 SD_SF_DETECT_TIME_7 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10-7. Reset 0/0 625/130
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Table 93. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-8) (R/W) Address (Hex) 1305 Bit 15 14:0 Name SD_SF_DETECT_UNIT_8 SD_SF_DETECT_TIME_8 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10-8 . Reset 0/0 5200/1300
Table 94. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-9) (R/W) Address (Hex) 1306 Bit 15 14:0 Name SD_SF_DETECT_UNIT_9 SD_SF_DETECT_TIME_9 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10 .
-9
Reset 1/0 21/10500
Table 95. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10-10) (R/W) Address (Hex) 1307 Bit 15 14:0 Name SD_SF_DETECT_UNIT_10 SD_SF_DETECT_TIME_10 Description Time Unit 0.5 ms(0)/1 s(1). Detection Time Value--BER: 1 x 10-10. Reset 1/1 170/41
Table 96. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-3) (R/W) Address (Hex) 1310 Bit 15:0 Name SD_SF_ERR_LIMIT_3 Description Detect Error Limit--BER: 1 x 10-3. Reset 4818/19453
Table 97. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-4) (R/W) Address (Hex) 1311 Bit 15:0 Name SD_SF_ERR_LIMIT_4 Description Detect Error Limit--BER: 1 x 10-4. Reset 862/3543
Table 98. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-5) (R/W) Address (Hex) 1312 Bit 15:0 Name SD_SF_ERR_LIMIT_5 Description Detect Error Limit--BER: 1 x 10-5. Reset 81/358
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Microprocessor Interface (continued)
Table 99. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-6) (R/W) Address (Hex) 1313 Bit 15:0 Name SD_SF_ERR_LIMIT_6 Description Detect Error Limit--BER: 1 x 10-6. Reset 62/51
Table 100. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-7) (R/W) Address (Hex) 1314 Bit 15:0 Name SD_SF_ERR_LIMIT_7 Description Detect Error Limit--BER: 1 x 10-7. Reset 62/51
Table 101. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-8) (R/W) Address (Hex) 1315 Bit 15:0 Name SD_SF_ERR_LIMIT_8 Description Detect Error Limit--BER: 1 x 10-8. Reset 51/51
Table 102. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10-9) (R/W) Address (Hex) 1316 Bit 15:0 Name SD_SF_ERR_LIMIT_9 Description Detect Error Limit--BER: 1 x 10-9. Reset 40/40
Table 103. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-4) (R/W) Address (Hex) 1320 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_3 Description Clear Error Limit--BER: 1 x 10-4. Reset 957/3734
Table 104. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-5) (R/W) Address (Hex) 1321 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_4 Description Clear Error Limit--BER: 1 x 10-5. Reset 114/423
Table 105. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-6) (R/W) Address (Hex) 1322 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_5 Description Clear Error Limit--BER: 1 x 10-6. Reset 91/77
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Table 106. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-7) (R/W) Address (Hex) 1323 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_6 Description Clear Error Limit--BER: 1 x 10-7. Reset 91/77
Table 107. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-8) (R/W) Address (Hex) 1324 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_7 Description Clear Error Limit--BER: 1 x 10-8. Reset 77/77
Table 108. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-9) (R/W) Address (Hex) 1325 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_8 Description Clear Error Limit--BER: 1 x 10-9. Reset 63/63
Table 109. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10-10) (R/W) Address (Hex) 1326 Bit 15:0 Name SD_SF_CLR_ERR_LIMIT_9 Description Clear Error Limit--BER: 1 x 10-10. Reset 52/51
LTE Receive Channel 1, 2, 3, and 4 Registers
s s
Base address: 0x1400 Channel offset: 0x0100
Table 110. LTE Receive Channel 1 Provisioning (R/W) Address (Hex) 1400 Bit 15:8 7 Name -- B1_ERROR_MASK_EN Description Reset 0 0
6
5
4
3 2 1 0 122
Unused. Program to zero. B1 Error Mask Enable. 1 = ROHDAT B1 byte error mask. 0 = ROHDAT B1 byte. B1_BIP_MODE_1 B1 BIP-8 Mode. 1 = Block error mode. 0 = Bit error mode. K_VALIDATE_LIMIT_SEL_1 K1K2 Validate Select. 1 = Five consecutive frames. 0 = Three consecutive frames. RX_FRM_EN_1 RFRM Output Enable. 1 = Validated S1 byte. 0 = 8 kHz signal. DESCRM_DIS_1 Disable Descrambling LTE Receive Input Signals. ENH_FRMG_CTL_1 Enable Enhanced Framing. SEF_AIS_DIS_1 Disable AIS Generation Due to Severely Errored Frame (SEF). LOF_AIS_DIS_1 Disable AIS Generation Due to Loss of Frame (LOF).
0
0
0
0 0 1 0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 111. LTE Receive Channel 1 Maintenance (R/W) Address (Hex) 1401 Bit 15:7 6 Name -- J_MSG_TYPE_1 Description Unused. Program to zero. J0 Message Type. 1 = SDH. 0 = SONET. J0 Message Mode. 1 = Validated. 0 = Provisioned. Signal Degrade Bit Error Rate. 4 = 1 x 10-9. 3 = 1 x 10-8. 2 = 1 x 10-7. 1 = 1 x 10-6. 0 = 1 x 10-5. Signal Fail Bit Error Rate. 2 = 1 x 10-5. 1 = 1 x 10-4. 0 = 1 x 10-3. Reset 0 0
5
J_MSG_MODE_1
1
4:2
SD_BER_1
0
1:0
SF_BER_1
0
Table 112. LTE Receive Channel 1 Loss-of-Signal (LOS) Threshold (R/W) Address (Hex) 1402 Bit 15:10 9:0 Name Description Reset 0 0x86
-- Unused. Program to zero. LTE_RX_1_LOS_THRESHOLD1 Threshold to Declare LOS (all zeros), Measured in Multiples of Eight R_CLK_n Cycles.
Table 113. LTE Receive Channel 1 K Byte Status (RO) Address (Hex) 1403 Bit 15:8 7:0 Name RX_K1_VALIDATED_BYTE_1 RX_K2_VALIDATED_BYTE_1 Description K1 Byte--Validated (3/5) K1 Bytes. K2 Byte--Validated (3/5) K2 Bytes. Reset 0 0
Table 114. LTE Receive Channel 1 S1 Byte Status (RO) Address (Hex) 1404 Bit 15:8 7:0 Name -- LTE_RX_1_RX_S1_BYTE_1 Description Unused. S1 Byte--Validated (7) S1 Bytes. Reset 0 0
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Table 115. LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) Address (Hex) 1405 Bit 15:5 4 3 2 1 0 Name -- SD_ALARM_1 SF_ALARM_1 RX_LINE_AIS_ALARM_1 LOF LOS Description Unused. May write ones on clear (W1C) if desired. Signal Degrade. Signal Fail. Line AIS. Loss of Frame. Loss of Signal. Reset 0 0 0 0 1 0
Table 116. LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask (R/W) Address (Hex) 1406 Bit 15:5 4 Name -- SD_ALARM_1_M Description Unused. Program to zero. Signal Degrade Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Signal Fail Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Line AIS Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Frame Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Signal Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
3
SF_ALARM_1_M
0
2
RX_LINE_AIS_ALARM_1_M
0
1
LOF_M
0
0
LOS_M
0
Table 117. LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO) Address (Hex) 1407 Bit 15:3 2 1 0 Name -- AISL_PER LOF_PER LOS_PER Description Unused. Persistent Line AIS Alarm. Persistent LOF Alarm. Persistent LOS Alarm. Reset 0 0 1 0
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Microprocessor Interface (continued)
Table 118. LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) Address (Hex) 1408 Bit 15:11 10 9 8 7 6 5 4 3 2 1 0 Name -- RX_OH_MEM_PAR_ERR_1 J_MEM_PARITY_ERR_1 RX_S1_NEW_BYTE_RAW_INT_1 RX_K2_NEW_BYTE_RAW_INT_1 RX_K1_NEW_BYTE_RAW_INT_1 INCONSISTENT_APS_ALARM_1 CHANNEL_MISMATCH_ALARM_1 RX_LINE_RDI_ALARM_1 J_NEW_MSG_INT_1 J_MSG_MISMATCH_INT_1 SEF Description Unused. May write ones on clear (W1C) if desired. Receive Overhead Data (ROHDAT) Memory Parity Error. J0 Message Buffer Parity Error. New Validated S1 Byte Received. New Validated K2 Byte Received. New Validated K1 Byte Received. Inconsistent APS Byte Received. Receive/Transmit K1K2 Byte Channel Mismatch. Line Remote Defect Indication (RDI-L). New Validated J0 Message Received. Received J0 Message Mismatch (with expected message). Severely Errored Frame (SEF). Reset 0 0 0 0 0 0 0 0 0 0 0 1
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Table 119. LTE Receive Channel 1 Nonservice-Affecting Interrupt Mask (R/W) Address (Hex) 1409 Bit 15:11 10 Name Description Reset 0 0
9
8
7
6
5
4
3
2
1
0
-- Unused. Program to zero. RX_OH_MEM_PAR_ERR_1_M Receive Overhead Data (ROHDAT) Memory Parity Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. J_MEM_PARITY_ERR_1_M J0 Message Buffer Parity Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. RX_S1_NEW_BYTE_RAW_ New Validated S1 Byte Received Interrupt INT_1_M Mask. 1 = Enable interrupt. 0 = Mask interrupt. RX_K2_NEW_BYTE_RAW_ New Validated K2 Byte Received Interrupt INT_1_M Mask. 1 = Enable interrupt. 0 = Mask interrupt. RX_K1_NEW_BYTE_RAW_ New Validated K1 Byte Received Interrupt INT_1_M Mask. 1 = Enable interrupt. 0 = Mask interrupt. INCONSISTENT_APS_ALARM_ Inconsistent APS Byte Received Interrupt 1_M Mask. 1 = Enable interrupt. 0 = Mask interrupt. CHANNEL_MISMATCH_ Receive/Transmit K1K2 Byte Channel MisALARM_1_M match Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. RX_LINE_RDI_ALARM_1_M Line Remote Defect Indication (RDI-L) Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. J_NEW_MSG_INT_1_M New Validated J0 Message Received Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. J_MSG_MISMATCH_INT_1_M Received J0 Message Mismatch (with Expected) Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. SEF_M Severely Errored Frame (SEF) Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
0
0
0
0
0
0
0
0
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Microprocessor Interface (continued)
Table 120. LTE Receive Channel 1 Nonservice-Affecting Persistency Alarm (RO) Address (Hex) 140A Bit 15:6 5 4 3 2:0 Name Description Reset 0 0 0 0 0
-- Unused. INCONSISTENT_APS_PER_1 Inconsistent APS Byte Received. CHANNEL_MISMATCH_PER_1 Receive/Transmit K1K2 Byte Channel Mismatch. RX_LINE_RDI_PER_1 Line Remote Defect Indication (RDI-L). -- Unused.
Table 121. LTE Receive Channel 1 Performance Monitoring (RO) Address (Hex) 140B Bit 15:5 4 3 2 1 0 Name -- RX_LINE_RDI_PM_1 SEF_PM RX_LINE_AIS_PM_1 LOF_PM LOS_PM Description Unused. Line Remote Defect Indication (RDI-L) Detect Last Second. Severely Errored Frame (SEF) Detect Last Second. Line AIS (AIS-L) Detect Last Second. Loss of Frame (LOF) Detect Last Second. Loss of Signal (LOS) Detect Last Second. Reset 0 0 0 0 0 0
Table 122. LTE Receive Channel 1 REI-L Performance Monitoring (L) (RO) Address (Hex) 140C Bit 15:0 Name REI_L_REG_1_L Description Remote Error Indications in Last Second (LSW). Reset 0
Table 123. LTE Receive Channel 1 REI-L Performance Monitoring (U) (RO) Address (Hex) 140D Bit 15:5 4:0 Name -- REI_L_REG_1_U Description Unused. Remote Error Indications in Last Second (MSW). Reset 0 0
Table 124. LTE Receive Channel 1 CV-L Performance Monitoring (L) (RO) Address (Hex) 140E Bit 15:0 Name CV_L_REG_1_L Description Line BIP-8 Errors (B2) Errors in Last Second (LSW). Reset 0
Table 125. LTE Receive Channel 1 CV-L Performance Monitoring (U) (RO) Address (Hex) 140F Bit 15:8 7:0 Name -- CV_L_REG_1_U Description Unused. Line BIP-8 Errors (B2) Errors in Last Second (MSW). Reset 0 0 127
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 126. LTE Receive Channel 1 CV-S Performance Monitoring (RO) Address (Hex) 1410 Bit 15:0 Name CV_S_REG_1 Description Section BIP-8 Errors (B1) in Last Second. Reset 0
LTE Transmit Common Registers
Table 127. LTE Transmit--Frame Pulse Offset Count (R/W) Address (Hex) 1B00 Bit 15 14 13:0 Name ADD_TX_SYNC TX_FRM_DEJITTER_EN LTE_TX_FRM_OFFSET_ COUNT Description Transmit Add Synchronization Enable (ADD_TX_SYNC = 0). TFRM Dejitter Circuit Enable (bit 15 set to 0). Frame Pulse Offset Position (in Multiples of Eight T_CLK Clock Cycles). See the Add Interface Framing (A1 and A2) section on page 82 for details. Reset 0 0 0
Table 128. LTE Transmit--Add Interface Self-Sync Option (R/W) Address (Hex) 1B00 Bit 15 14:4 3:0 Name ADD_TX_SYNC -- LTE_TX_FRM_ADDCHNL_ SEL Description Transmit Add Synchronization Enable (ADD_TX_SYNC = 1). Unused (when bit 15 set to 1). When Bit 15 is Set to 1, Bits 3:0 Select Transmit Frame Sync Add Channel (1--16). See the Add Interface Framing (A1 and A2) section on page 82 for details. Reset 1 0 0
Table 129. LTE Transmit--B1 Corrupt Frame Count (R/W) Address (Hex) 1B01 Bit 15:13 12:0 Name Description Reset 0 0
-- Unused. Program to zero. LTE_TX_B1_NUM_CORRUPT_ Number of Frames to Corrupt Inserted FRAMES B1 Byte. Used by register 0x1C00. See Table 135 on page 130.
Table 130. LTE Transmit--B2 Corrupt Frame Count (R/W) Address (Hex) 1B02 Bit 15:13 12:0 Name Description Reset 0 0
-- Unused. Program to zero. LTE_TX_B2_NUM_CORRUPT_ Number of Frames to Corrupt Inserted B2 FRAMES Bytes. Used by register 0x1C00. See Table 135 on page 130. B2 Error Serial Access. Enabled when value is greater than or equal to 8064(dec).
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Microprocessor Interface (continued)
Table 131. LTE Transmit--M1 Corrupt Frame Count (R/W) Address (Hex) 1B03 Bit 15:13 12:0 Name Description Reset 0 0
-- Unused. Program to zero. LTE_TX_M1_NUM_CORRUP Number of Frames to Corrupt Inserted M1 T_FRAMES Byte. Used by register 0x1C00. See Table 135 on page 130.
Table 132. LTE Transmit--TFRM S1 Byte (RO) Address (Hex) 1B04 Bit 15:8 7:0 Name Description Reset 0 0
-- Unused. LTE_TX_S1_BYTE_TX_FRM Validated S1 Byte from TFRM Signal. See the Synchronization Status (S1) section on page 91 for details.
Table 133. LTE Transmit--Interrupt Alarm Register (W1C) Address (Hex) 1B05 Bit 15:4 3 Name -- Description Reset 0 0
2
1
0
Unused. May write ones on clear (W1C) if desired. TX_FRM_RESYNC TFRM Resynchronization Alarm. Latched alarm. See the Add Interface Framing (A1 and A2) section on page 82 for details. TX_J0_MEM_PARITY_ERR Transmit J0 Memory Parity Error. See the Section Trace/Section Growth (J0/Z0) section on page 86 for details. TX_FRM_S1_BYTE_INVALID Valid S1 Byte Not Received. See the Synchronization Status (S1) section on page 91 for details. TX_FRM_LOF TFRM Loss of Frame. See the Add Interface Framing (A1 and A2) section on page 82 for details.
0
0
0
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Table 134. LTE Transmit--Interrupt Mask Register (R/W) Address Bit (Hex) 1B06 15:4 3 Name -- TX_FRM_RESYNC_M Description Reset 0 0
2
1
0
Unused. Program to zero. TFRM Resynchronization Alarm Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. TX_J0_MEM_PARITY_ERR_M Transmit J0 Memory Parity Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. TX_FRM_S1_BYTE_INVALID_M Valid S1 Byte Not Received Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. TX_FRM_LOF_M TFRM Loss of Frame Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
0
LTE Transmit Channel Registers
s s
Base address: 0x1C00 Channel offset: 0x0100
Table 135. LTE Transmit Channel 1 Provisioning (R/W) Address (Hex) 1C00 Bit 15:11 10 9 Name -- TX_SS_OVERWRITE_EN Description Reset 0 0 0
8 7 6 5 4
3
2
1
0 130
Unused. Program to zero. Enable Insertion of Defined SS Bits in All of the Outgoing H1 Bytes. SS_MODE SS Bit Mode Define SS Bit. 1 = SDH (10). 0 = SONET (00). REGEN_LOOPBACK Powerup Default. LINE_TRANS_ONLY_EN Powerup Default. TOH_TRANS_EN Powerup Default. SCRM_DIS_1 Disable Scrambling on Transmit Data. M1_CORRUPT_EN_1 Enable Corruption of M1 Byte for N Frames. (The number of frames (N) is selected in register 0x1B03, Table 131 on page 129.) B2_CORRUPT_EN_1 Enable Corruption of B2 Bytes for N Frames. (The number of frames (N) is selected in register 0x1B02, Table 130 on page 128.) B1_CORRUPT_EN_1 Enable Corruption of B1 Byte for N Frames. (The number of frames (N) is selected in register 0x1B01, Table 129 on page 128.) TX_FRAMING_MODE_1 Framing Mode. Enhanced mode is normally used only when in STS-192 mode. 1 = Enhanced. 0 = Normal. TX_TOH_DATA_INSERT_1 Enable Transport Overhead Data (TOHDAT) Insertion.
0 0 0 0 0
0
0
0
0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 136. LTE Transmit Bit Assignment Bit 7 Bit 6 LINE_TRANS_ONLY_EN TOH_TRANS_EN X 0 1
Note: X indicates either value.
Description Section and line terminated (pointer processor state dependent on DRPBYP pin). Full section and line overhead transparency (pointer processor bypassed automatically). Line overhead transparency section is terminated (pointer processor bypassed).
0 1 1
Table 137. LTE Transmit Channel 1 Maintenance (R/W) Address Bit (Hex) 1C01 Name Description Reset 0 0 0 0 0 0
15:6 -- Unused. Program to zero. 5 TX_J0_MSG_INSERT_EN_1 Enable Insertion of Provisioned J0 Message. 4 S1_BYTE_TX_FRM_INSERT_1 Insert Validated S1 Byte from TFRM. 3:2 TX_K_BYTES_SELECT_1 K Byte Select. SW(0)/Raw K Bytes(1)/Validated K Bytes(2). 1 RDI_L_SELECT_1 Enable RDI-L Insertion. When set to 1, enables RDI-L when a condition arises to cause RDI-L. 0 TX_LINE_AIS_INSERT_1 Force Line AIS Insertion. Forces AIS_L Insertion when set to 1.
Table 138. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 (R/W) Address (Hex) 1C02 Bit 15:12 11:0 Name -- LTE_TX_1_UNEQ_P_EN_1 Description Unused. Program to zero. Insert UNEQ-P on Specific STS-1 (1 to 12). Reset 0 0
Table 139. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2 (R/W) Address (Hex) 1C03 Bit 15:12 11:0 Name -- LTE_TX_1_UNEQ_P_EN_2 Description Unused. Program to zero. Insert UNEQ-P on Specific STS-1 (13 to 24). Reset 0 0
Table 140. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3 (R/W) Address (Hex) 1C04 Bit 15:12 11:0 Name -- LTE_TX_1_UNEQ_P_EN_3 Description Unused. Program to zero. Insert UNEQ-P on Specific STS-1 (25 to 36). Reset 0 0
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Table 141. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4 (R/W) Address (Hex) 1C05 Bit 15:12 11:0 Name -- LTE_TX_1_UNEQ_P_EN_4 Description Unused. Program to zero. Insert UNEQ-P on Specific STS-1 (37 to 48). Reset 0 0
Table 142. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 (R/W) Address (Hex) 1C06 Bit 15:12 11:0 Name -- LTE_TX_1_PATH_AIS_EN_1 Description Unused. Program to zero. Insert AIS-P on Specific STS-1 (1 to 12). Reset 0 0
Table 143. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2 (R/W) Address (Hex) 1C07 Bit 15:12 11:0 Name -- LTE_TX_1_PATH_AIS_EN_2 Description Unused. Program to zero. Insert AIS-P on Specific STS-1 (13 to 24). Reset 0 0
Table 144. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3 (R/W) Address (Hex) 1C08 Bit 15:12 11:0 Name -- LTE_TX_1_PATH_AIS_EN_3 Description Unused. Program to zero. Insert AIS-P on Specific STS-1 (25 to 36). Reset 0 0
Table 145. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4 (R/W) Address (Hex) 1C09 Bit 15:12 11:0 Name -- LTE_TX_1_PATH_AIS_EN_4 Description Unused. Program to zero. Insert AIS-P on Specific STS-1 (37 to 48). Reset 0 0
Table 146. LTE Transmit Channel 1 K1K2 Byte Insert Values (R/W) Address (Hex) 1C0A Bit 15:8 7:0 Name TX_K1_SW_BYTE_1 TX_K2_SW_BYTE_1 Description K1 Byte Value to Insert. K2 Byte Value to Insert. Reset 0 0
Table 147. LTE Transmit Channel 1 S1 Byte Insert Value (R/W) Address (Hex) 1C0B Bit 15:8 7:0 Name -- LTE_TX_1_S1_DATA_1 Description Unused. Program to zero. S1 Byte Value to Insert. Reset 0 0
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Microprocessor Interface (continued)
Table 148. LTE Transmit Channel 1 Interrupt Alarm (W1C) Address (Hex) 1C0C Bit 15:2 1 0 Name -- Description Unused. May write ones on clear (W1C) if desired. Reset 0 0 0
TX_OH_MEM_PARITY_ERR_1 Transport Overhead Data Memory Parity Error. TX_DATA_PAR_ERR_1 Transmit Data Path Internal Parity Error.
Table 149. LTE Transmit Channel 1 Interrupt Alarm Mask (R/W) Address (Hex) 1C0D Bit 15:2 1 Name -- Description Unused. Program to zero. Reset 0 0
TX_OH_MEM_PARITY_ERR_1_M Transport Overhead Data Memory Parity Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. TX_DATA_PAR_ERR_1_M Transmit Data Path Internal Parity Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
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Microprocessor Interface (continued)
Equipment (EQPT) Registers
EQPT Common Registers Table 150. EQPT Interrupt Status (RO) Address (Hex) 2000 Bit 15:13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- Unused. Description Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EQPT_RX_DRP_NSA_4 Receive Drop STS-48 Channel Nonservice-Affecting Alarms. EQPT_RX_DRP_NSA_3 Receive Drop STS-48 Channel Nonservice-Affecting Alarms. EQPT_RX_DRP_NSA_2 Receive Drop STS-48 Channel Nonservice-Affecting Alarms. EQPT_RX_DRP_NSA_1 Receive Drop STS-48 Channel Nonservice-Affecting Alarms. EQPT_RX_DRP_SA Receive Drop Common Service-Affecting Alarms. EQPT_TX_ADD_NSA_4 Transmit Add STS-48 Channel 4 Nonservice-Affecting Alarms. EQPT_TX_ADD_NSA_3 Transmit Add STS-48 Channel 3 Nonservice-Affecting Alarms. EQPT_TX_ADD_NSA_2 Transmit Add STS-48 Channel 2 Nonservice-Affecting Alarms. EQPT_TX_ADD_NSA_1 Transmit Add STS-48 Channel 1 Nonservice-Affecting Alarms. EQPT_TX_ADD_SA_4 EQPT_TX_ADD_SA_3 EQPT_TX_ADD_SA_2 EQPT_TX_ADD_SA_1 Transmit Add STS-48 Channel 4 Service-Affecting Alarms. Transmit Add STS-48 Channel 3 Service-Affecting Alarms. Transmit Add STS-48 Channel 2 Service-Affecting Alarms. Transmit Add STS-48 Channel 1 Service-Affecting Alarms.
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Microprocessor Interface (continued)
Table 151. EQPT Interrupt Mask (R/W) Address (Hex) 2001 Bit 15:13 12 Name Description Reset 0 0
11
10
9
8
7
6
5
4
3
2
-- Unused. Program to zero. EQPT_RX_DRP_NSA_4_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_RX_DRP_NSA_3_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_RX_DRP_NSA_2_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_RX_DRP_NSA_1_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_RX_DRP_SA_M Receive Drop Common Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_TX_ADD_NSA_4_M Transmit Add STS-48 Channel 4 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_TX_ADD_NSA_3_M Transmit Add STS-48 Channel 3 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_TX_ADD_NSA_2_M Transmit Add STS-48 Channel 2 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_TX_ADD_NSA_1_M Transmit Add STS-48 Channel 1 Nonservice-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_TX_ADD_SA_4_M Transmit Add STS-48 Channel 4 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. EQPT_TX_ADD_SA_3_M Transmit Add STS-48 Channel 3 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
0
0
0
0
0
0
0
0
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Table 151. EQPT Interrupt Mask (R/W) (continued) Address (Hex) 2001 Bit 1 Name EQPT_TX_ADD_SA_2_M Description Transmit Add STS-48 Channel 2 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Transmit Add STS-48 Channel 1 Service-Affecting Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
0
EQPT_TX_ADD_SA_1_M
0
Table 152. Receive Drop Common Service-Affecting Alarm (W1C) Address (Hex) 2002 Bit 15:1 0 Name -- DFRM_LOSS Description Unused. May write ones on clear (W1C) if desired. Loss of DFRM Signal. 1 = Loss of DFRM. 0 = DFRM detected. Reset 0 0
Table 153. Receive Drop Common Service-Affecting Alarm Mask (R/W) Address (Hex) 2003 Bit 15:1 0 Name -- DFRM_LOSS_M Description Unused. Program to zero. Loss of DFRM Signal Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
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Microprocessor Interface (continued)
EQPT Receive Drop STS-48 Channel Registers 1--4
s s
Base address: 0x2400 Channel offset: 0x0100
Table 154. Receive Drop STS-48 Channel Provisioning Register 1 (R/W) Address (Hex) 2400 Bit 15:2 1 0 Name -- B1_ERROR_INS SCRM_DISABLE Description Unused. Program to zero. Insert BIP-8 Error. 1 = Insert a BIP-8 error. Scrambler Disable. 1 = Disables the receive drop interface scrambler. 0 = Enables the receive drop interface scrambler. Reset 0 0 0
Table 155. J0 Trace--STS-12 Channel 1 (R/W) Address (Hex) 2401 Bit 15:8 7:0 Name -- J0_BYTE_1 Description Unused. Program to zero. J0 Byte for Insert in STS-12 Channel 1. Reset 0 1
Table 156. J0 Trace--STS-12 Channel 2 (R/W) Address (Hex) 2402 Bit 15:8 7:0 Name -- J0_BYTE_2 Description Unused. Program to zero. J0 Byte for Insert in STS-12 Channel 2. Reset 0 2
Table 157. J0 Trace--STS-12 Channel 3 (R/W) Address (Hex) 2403 Bit 15:8 7:0 Name -- J0_BYTE_3 Description Unused. Program to zero. J0 Byte for Insert in STS-12 Channel 3. Reset 0 3
Table 158. J0 Trace--STS-12 Channel 4 (R/W) Address (Hex) 2404 Bit 15:8 7:0 Name -- J0_BYTE_4 Description Unused. Program to zero. J0 Byte for Insert in STS-12 Channel 4. Reset 0 4
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Microprocessor Interface (continued)
Table 159. Receive Drop STS-48 Channel Nonservice-Affecting Alarm (W1C) Address (Hex) 2405 Bit 15:5 4 3 2 1 0 Name -- RX_DATA_PAR_ERR_4 RX_DATA_PAR_ERR_3 RX_DATA_PAR_ERR_2 RX_DATA_PAR_ERR_1 RX_DATA_PAR_ERR_0 Description Unused. May write ones on clear (W1C) if desired. Data Path Parity Error Timing Control Channel. Data Path Parity Error STS-12 Channel 3. Data Path Parity Error STS-12 Channel 2. Data Path Parity Error STS-12 Channel 1. Data Path Parity Error STS-12 Channel 0. Reset 0 0 0 0 0 0
Table 160. Receive Drop STS-48 Channel Nonservice Affecting Alarm Mask (R/W) Address (Hex) 2406 Bit 15:5 4 Name -- RX_DATA_PAR_ERR_4_M Description Unused. Program to zero. Data Path Parity Error Timing Control Channel Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Data Path Parity Error STS-12 Channel 3 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Data Path Parity Error STS-12 Channel 2 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Data Path Parity Error STS-12 Channel 1 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Data Path Parity Error STS-12 Channel 0 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
3
RX_DATA_PAR_ERR_3_M
0
2
RX_DATA_PAR_ERR_2_M
0
1
RX_DATA_PAR_ERR_1_M
0
0
RX_DATA_PAR_ERR_0_M
0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
EQPT Transmit Add STS-48 Channel Registers 1--4
s s
Base address: 0x2C00 Channel offset: 0x0100
Table 161. Transmit Add STS-48 Channel Provisioning (R/W) Address (Hex) 2C00 Bit 15:2 1 Name Description Reset 0 0
0
-- Unused. Program to zero. FRC_ADD_BUFFER_OVRFLW Force Add Buffer Overflow/Underflow Alarm in STS-12s. 1 = Force an add buffer overflow/underflow alarm. 0 = Normal operation. DESCRM_DISABLE Descrambler Disable. 1 = Disables the transmit add interface scrambler. 0 = Enables the transmit add interface scrambler.
0
Table 162. J0 Status Register--1 (RO) Address (Hex) 2C01 Bit 15:8 7:0 Name -- J0_BYTE--STS-12 Channel 1 Unused. J0 Status Byte. Description Reset 0 0
Table 163. J0 Status Register--2 (RO) Address (Hex) 2C02 Bit 15:8 7:0 Name -- J0_BYTE--STS-12 Channel 2 Unused. J0 Status Byte. Description Reset 0 0
Table 164. J0 Status Register--3 (RO) Address (Hex) 2C03 Bit 15:8 7:0 Name -- J0_BYTE--STS-12 Channel 3 Unused. J0 Status Byte. Description Reset 0 0
Table 165. J0 Status Register--4 (RO) Address (Hex) 2C04 Bit 15:8 7:0 Name -- J0_BYTE--STS-12 Channel 4 Unused. J0 Status Byte. Description Reset 0 0
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Microprocessor Interface (continued)
Table 166. AIS Insert Status Register, STS-12 Channel #1 (RO) Address (Hex) 2C05 Bit 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- AIS_INSERT11 AIS_INSERT10 AIS_INSERT9 AIS_INSERT8 AIS_INSERT7 AIS_INSERT6 AIS_INSERT5 AIS_INSERT4 AIS_INSERT3 AIS_INSERT2 AIS_INSERT1 AIS_INSERT0 Description Unused. STS Channel #12 AIS Insert Status. STS Channel #11 AIS Insert Status. STS Channel #10 AIS Insert Status. STS Channel #9 AIS Insert Status. STS Channel #8 AIS Insert Status. STS Channel #7 AIS Insert Status. STS Channel #6 AIS Insert Status. STS Channel #5 AIS Insert Status. STS Channel #4 AIS Insert Status. STS Channel #3 AIS Insert Status. STS Channel #2 AIS Insert Status. STS Channel #1 AIS Insert Status. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 167. AIS Insert Status Register, STS-12 Channel #2 (RO) Address (Hex) 2C06 Bit 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- AIS_INSERT11 AIS_INSERT10 AIS_INSERT9 AIS_INSERT8 AIS_INSERT7 AIS_INSERT6 AIS_INSERT5 AIS_INSERT4 AIS_INSERT3 AIS_INSERT2 AIS_INSERT1 AIS_INSERT0 Description Unused. STS Channel #12 AIS Insert Status. STS Channel #11 AIS Insert Status. STS Channel #10 AIS Insert Status. STS Channel #9 AIS Insert Status. STS Channel #8 AIS Insert Status. STS Channel #7 AIS Insert Status. STS Channel #6 AIS Insert Status. STS Channel #5 AIS Insert Status. STS Channel #4 AIS Insert Status. STS Channel #3 AIS Insert Status. STS Channel #2 AIS Insert Status. STS Channel #1 AIS Insert Status. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 168. AIS Insert Status Register, STS-12 Channel #3 (RO) Address (Hex) 2C07 Bit 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- AIS_INSERT11 AIS_INSERT10 AIS_INSERT9 AIS_INSERT8 AIS_INSERT7 AIS_INSERT6 AIS_INSERT5 AIS_INSERT4 AIS_INSERT3 AIS_INSERT2 AIS_INSERT1 AIS_INSERT0 Description Unused. STS Channel #12 AIS Insert Status. STS Channel #11 AIS Insert Status. STS Channel #10 AIS Insert Status. STS Channel #9 AIS Insert Status. STS Channel #8 AIS Insert Status. STS Channel #7 AIS Insert Status. STS Channel #6 AIS Insert Status. STS Channel #5 AIS Insert Status. STS Channel #4 AIS Insert Status. STS Channel #3 AIS Insert Status. STS Channel #2 AIS Insert Status. STS Channel #1 AIS Insert Status. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 169. AIS Insert Status Register, STS-12 Channel #4 (RO) Address (Hex) 2C08 Bit 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- AIS_INSERT11 AIS_INSERT10 AIS_INSERT9 AIS_INSERT8 AIS_INSERT7 AIS_INSERT6 AIS_INSERT5 AIS_INSERT4 AIS_INSERT3 AIS_INSERT2 AIS_INSERT1 AIS_INSERT0 Description Unused. STS Channel #12 AIS Insert Status. STS Channel #11 AIS Insert Status. STS Channel #10 AIS Insert Status. STS Channel #9 AIS Insert Status. STS Channel #8 AIS Insert Status. STS Channel #7 AIS Insert Status. STS Channel #6 AIS Insert Status. STS Channel #5 AIS Insert Status. STS Channel #4 AIS Insert Status. STS Channel #3 AIS Insert Status. STS Channel #2 AIS Insert Status. STS Channel #1 AIS Insert Status. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
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Microprocessor Interface (continued)
Table 170. Transmit Add STS-48 Channel Alarm (W1C) Address (Hex) 2C09 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- B1_ERROR_4 Description Unused. May write ones on clear (W1C) if desired. BIP-8 Error STS-12 Channel 4--NSA. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADD12_BUFFER_OVRFLW_4 Synchronization Buffer Overflow/Underflow STS-12 Channel 4--NSA. OOF_4 -- B1_ERROR_3 Out-of-Frame Alarm STS-12 Channel 4--SA. Unused. May write ones on clear (W1C) if desired. BIP-8 Error STS-12 Channel 3--NSA.
ADD12_BUFFER_OVRFLW_3 Synchronization Buffer Overflow/Underflow STS-12 Channel 3--NSA. OOF_3 -- B1_ERROR_2 Out-of-Frame Alarm STS-12 Channel 3--SA. Unused. May write ones on clear (W1C) if desired. BIP-8 Error STS-12 Channel 2--NSA.
ADD12_BUFFER_OVRFLW_2 Synchronization Buffer Overflow/Underflow STS-12 Channel 2--NSA. OOF_2 -- B1_ERROR_1 Out-of-Frame Alarm STS-12 Channel 2--SA. Unused. May write ones on clear (W1C) if desired. BIP-8 Error STS-12 Channel 1--NSA.
ADD12_BUFFER_OVRFLW_1 Synchronization Buffer Overflow/Underflow STS-12 Channel 1--NSA. OOF_1 Out-of-Frame Alarm STS-12 Channel 1--SA.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 171. Transmit Add STS-48 Channel Alarm Mask (R/W) Address (Hex) 2C0A Bit 15 14 Name -- B1_ERROR_4_M Description Unused. Program to zero. BIP-8 Error STS-12 Channel 4--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Synchronization Buffer Overflow/Underflow STS-12 Channel 4--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Out-of-Frame Alarm STS-12 Channel 4--SA interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unused. Program to zero. BIP-8 Error STS-12 Channel 3--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Synchronization Buffer Overflow/Underflow STS-12 Channel 3--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Out-of-Frame Alarm STS-12 Channel 3--SA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unused. Program to zero. BIP-8 Error STS-12 Channel 2--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Synchronization Buffer Overflow/Underflow STS-12 Channel 2--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Out-of-Frame Alarm STS-12 Channel 2--SA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unused. Program to zero. BIP-8 Error STS-12 Channel 1--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Synchronization Buffer Overflow/Underflow STS-12 Channel 1--NSA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Out-of-Frame Alarm STS-12 Channel 1--SA Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
13
ADD12_BUFFER_ OVRFLW_4_M
0
12
OOF_4_M
0
11 10
-- B1_ERROR_3_M
0 0
9
ADD12_BUFFER_ OVRFLW_3_M
0
8
OOF_3_M
0
7 6
-- B1_ERROR_2_M
0 0
5
ADD12_BUFFER_ OVRFLW_2_M
0
4
OOF_2_M
0
3 2
-- B1_ERROR_1_M
0 0
1
ADD12_BUFFER_ OVRFLW_1_M
0
0
OOF_1_M
0
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Data Sheet May 2003
Microprocessor Interface (continued)
Path Overhead (POH) Registers
Registers pertaining to the path are organized as shown in Figure 11. As can be seen, some functions are performed at the STS-1 level. Registers for these functions are arranged as a group of 12 and then grouped with functions that are performed at the STS-12 level. This group is repeated 16 times in the memory map. Functions that are performed at the STS-48 level are also grouped together. In the diagram, the numbers to the top left of each box represent the base address of registers in the first occurrence of that block of registers. The numbers to the bottom right represent the offset to the next occurrence of that block of registers. Note that register offsets refer to SONET number, not interleave order (i.e., STS-1 number two is one offset from STS-1 number 1). For example, to find the base address of the STS-1 level registers for STS-1 number 77, take 0x3010, add six times 0x0100 (since STS-1 number 77 is in the seventh STS-12), and then add 4 times 0x0010 (since STS-1 number 77 is the fifth STS-1 in the STS-12), and the result is 0x3650.
0X4000 CHIP (STS-192) LEVEL REGISTERS 0X4400 STS-48 LEVEL REGISTERS +0X0100 0X3000 STS-12 LEVEL REGISTERS 0X3010 STS-1 LEVEL REGISTERS 12 16 4
+0X0010
+0X0100
5-9097(F)r.1
Figure 11. Path Register Structure
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
STS-12, STS-1 Level POH Registers
s s s
Base address: 0x3000 STS-12 channel offset: 0x0100 STS-1 channel offset: 0x0010
Table 172. STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 (R/W) Address (Hex) 3000 Bit 15:4 5 Name -- AUTO_AIS_DIS Description Unused. Program to zero. Disable Automatic AIS Insertion. Note: It is recommended that automatic AIS insertion remain enabled unless in pointer generator bypass mode. 1 = Disable automatic AIS insertion. 0 = Enable automatic AIS insertion. Pointer Increment/Decrement Standard. 1 = SONET. The 8 of 10 rule will be used. Eight of the ten I and D bits must be correct for the pointer to be considered an increment or decrement. 0 = SDH. The 3 of 5 rule is used. Three of the five I and D bits must be correct for the pointer to be considered an increment or decrement. STS-1 Increment/Decrement Binning Select. Reset 0 0
4
INT_SONET_SDH
0
3:0
INT_INC_BIN
1
Table 173. STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 (R/W) Address (Hex) 3001 Bit 15:12 11 10:0 Name -- PP_CH_SW_AIS_INS_12 PP_CH_SW_AIS_INS_11-- PP_CH_SW_AIS_INS_1 Description Unused. Program to zero. STS-1 #12 AIS Insert. STS-1 #11 to STS-1 #1 AIS Insert. Reset 0 0 0
Table 174. STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) Address (Hex) 3002 Bit 15:11 10:0 Name -- PP_CH_INT_INC_PM Description Unused. Last Second Increments on Selected Pointer Interpreter. Reset 0 0
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Data Sheet May 2003
Microprocessor Interface (continued)
Table 175. STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) Address (Hex) 3003 Bit 15:11 10:0 Name -- PP_CH_INT_DEC_PM Description Unused. Last Second Decrements on Selected Pointer Interpreter. Reset 0 0
Table 176. STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) Address (Hex) 3004 Bit 15:11 10:0 Name -- PP_CH_GEN_INC_PM Description Unused. Last Second Increments on Selected Pointer Generator. Reset 0 0
Table 177. STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) Address (Hex) 3005 Bit 15:11 10:0 Name -- PP_CH_GEN_DEC_PM Description Unused. Last Second Decrements on Selected Pointer Generator. Reset 0 0
Table 178. STS-1 #1 Path Overhead Provisioning (R/W) Address (Hex) 3010 Bit 15:8 7:2 1 Name PROV_STS1_EXP_C2 -- CNT_BLK_ERRS Description Expected C2 Byte. Unused. Program to zero. Count B3 BIP-8 Errors, and G1 RDI-P and REI-P Errors. 1 = Block. 0 = Bit. Enable Payload Defect Indicator. Reset 0 0 0
0
PDI_EN
0
Table 179. STS-1 #1 Path Overhead Maintenance (R/W) Address (Hex) 3011 Bit 15:4 3 2:0 Name -- SD_INSERT SF_THRESH_SEL Description Unused. Program to zero. Insert Signal Degrade. Signal Fail Threshold Select (selects 1 of 8 SF detect/clear register sets at STS-192 level). Reset 0 0 0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 180. STS-1 #1 Path Overhead Status (RO) Address (Hex) 3012 Bit 15:11 10:8 7:0 Name -- RCV_RDI_CODE RCV_C2_BYTE Description Unused. Received RDI-P Code (currently validated (raw) RDI-P; may differ from PM register). Received C2 Byte. Reset 0 0 0
Table 181. STS-1 #1 Alarm Interrupt Status (W1C) Address (Hex) 3013 Bit 15:7 6 5 4 3 2 1 0 Name -- ES_OVRUN SIG_FAIL RDI_P PLM_P UNEQ_P AIS_P LOP_P Description Unused. May write ones on clear (W1C) if desired. Elastic Store Overrun/Underrun. Signal Fail. Remote Defect Indicator. Payload Label Mismatch. Unequipped Received. AIS Received. Loss of Pointer. Reset 0 0 0 0 0 0 0 0
Table 182. STS-1 #1 Alarm Interrupt Status Mask (R/W) Address (Hex) 3014 Bit 15:7 6 Name -- ES_OVRUN_M Description Unused. Program to zero. Elastic Store Overrun/Underrun Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Signal Fail Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Remote Defect Indicator Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Payload Label Mismatch Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unequipped Received Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. AIS Received Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Loss of Pointer Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
5
SIG_FAIL_M
0
4
RDI_P_M
0
3
PLM_P_M
0
2
UNEQ_P_M
0
1
AIS_P_M
0
0
LOP_P_M
0
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Data Sheet May 2003
Microprocessor Interface (continued)
Table 183. STS-1 #1 Alarm Persistency (RO) Address (Hex) 3015 Bit 15:5 4 3 2 1 0 Name -- RDI_P_PERS PLM_P_PERS UNEQ_P_PERS AIS_P_PERS LOP_P_PERS Description Unused. Remote Defect Indicator Persistent. Payload Label Mismatch Persistent. Unequipped Received Persistent. AIS Received Persistent. Loss of Pointer Persistent. Reset 0 0 0 0 0 0
Table 184. STS-1 #1 PM Last Second Indicators (RO) Address (Hex) 3016 Bit 15:7 6 5 4 3 2 1 0 Name -- RDI_ONE_BIT ERDI_PYLD ERDI_CONN ERDI_SRVR UNEQ AIS LOP Description Unused. 1-bit RDI-P Defect. ERDI-P Payload Defect. ERDI-P Connectivity Defect. ERDI-P Server Defect. UNEQ-P Received. AIS-P Received. Loss of Pointer. Reset 0 0 0 0 0 0 0 0
Table 185. STS-1 #1 Last Second CV-P Count (RO) Address (Hex) 3017 Bit 15:0 Name PM_STS1_CVP_CNT CV-P Count. Description Reset 0
Table 186. STS-1 #1 Last Second REI-P Count (RO) Address (Hex) 3018 Bit 15:0 Name PM_STS1_REIP_CNT REI-P Count. Description Reset 0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
STS-192 Level POH Registers
s
Base address: 0x4000
Table 187. Path Overhead (POH) Interrupt Status (RO) Address (Hex) 4000 Bit 15 14 13 12 11:0 Name STS48_CH4_ALARMS4 STS48_CH4_ALARMS3 STS48_CH4_ALARMS2 STS48_CH4_ALARMS1 STS1_CH_ALARMS Description STS-48 Channel 4 Path Alarms. STS-48 Channel 3 Path Alarms. STS-48 Channel 2 Path Alarms. STS-48 Channel 1 Path Alarms. STS-1 Channel Alarms (points to registers consolidating alarms per STS-1). Reset 0 0 0 0 0
Table 188. Path Overhead (POH) Interrupt Status Mask (R/W) Address (Hex) 4001 Bit 15 Name Description Reset 0
14
13
12
11:0
STS48_CH4_ALARMS4_M STS-48 Channel 4 Path Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS48_CH4_ALARMS3_M STS-48 Channel 3 Path Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS48_CH4_ALARMS2_M STS-48 Channel 2 Path Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS48_CH4_ALARMS1_M STS-48 Channel 1 Path Alarms Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS1_CH_ALARMS_M STS-1 Channel Alarms (points to registers consolidating alarms per STS-1) Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt.
0
0
0
0
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Table 189. STS-1 Signal Fail Detect Threshold, Window Size Select 0 (R/W) Address (Hex) 4002 Bit 15:14 13:9 8:0 Name SF_STS1_DET_WIN_SEL_0 -- SF_STS1_DET_THRESH_0 Description Window Size Select (chooses one of four SF window size registers). Unused. Program to zero. Detect Threshold. Reset 1 0 CF
Table 190. STS-1 Signal Fail Clear Threshold, Window Size Select 0 (R/W) Address (Hex) 4003 Bit 15:14 13:9 8:0 Name SF_STS1_CLR_WIN_SEL_0 -- SF_STS1_CLR_THRESH_0 Description Window Size Select (chooses one of four SF window size registers). Unused. Program to zero. Clear Threshold. Reset 2 0 113
Table 191. STS-1 Signal Fail Detect Threshold, Window Size Select 1 (R/W) Address (Hex) 4004 Bit 15:14 13:9 8:0 Name SF_STS1_DET_WIN_SEL_1 -- SF_STS1_DET_THRESH_1 Description Window Size Select (chooses one of four SF window size registers). Unused. Program to zero. Detect Threshold. Reset 2 0 DE
Table 192. STS-1 Signal Fail Clear Threshold, Window Size Select 1 (R/W) Address (Hex) 4005 Bit 15:14 13:9 8:0 Name SF_STS1_CLR_WIN_SEL_1 -- SF_STS1_CLR_THRESH_1 Description Window Size Select (chooses one of four SF window size registers). Unused. Program to zero. Clear Threshold. Reset 3 0 115
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 193. STS-Nc Signal Fail Detect Threshold, Window Size Select 2 (R/W) Address (Hex) 4006 Bit 15:14 13:0 Name SF_STSNC_DET_WIN_SEL_2 SF_STS1_DET_THRESH_2 Description Window Size Select (chooses one of four SF window size registers). Detect Threshold. Reset 1 233
Table 194. STS-Nc Signal Fail Clear Threshold, Window Size Select 2 (R/W) Address (Hex) 4007 Bit 15:14 13:0 Name SF_STSNC_CLR_WIN_SEL_2 SF_STS1_CLR_THRESH_2 Description Window Size Select (chooses one of four SF window size registers). Clear Threshold. Reset 2 30B
Table 195. STS-Nc Signal Fail Detect Threshold, Window Size Select 3 (R/W) Address (Hex) 4008 Bit 15:14 13:0 Name SF_STSNC_DET_WIN_SEL_3 SF_STS1_DET_THRESH_3 Description Window Size Select (chooses one of four SF window size registers). Detect Threshold. Reset 2 2B2
Table 196. STS-Nc Signal Fail Clear Threshold, Window Size Select 3 (R/W) Address (Hex) 4009 Bit 15:14 13:0 Name SF_STSNC_CLR_WIN_SEL_3 SF_STS1_CLR_THRESH_3 Description Window Size Select (chooses one of four SF window size registers). Clear Threshold. Reset 3 31B
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Table 197. STS-Nc Signal Fail Detect Threshold, Window Size Select 4 (R/W) Address (Hex) 400A Bit 15:14 13:0 Name SF_STSNC_DET_WIN_SEL_4 SF_STS1_DET_THRESH_4 Description Window Size Select (chooses one of four SF window size registers). Detect Threshold. Reset 1 3A3
Table 198. STS-Nc Signal Fail Clear Threshold, Window Size Select 4 (R/W) Address (Hex) 400B Bit 15:14 13:0 Name SF_STSNC_CLR_WIN_SEL_4 SF_STS1_CLR_THRESH_4 Description Window Size Select (chooses one of four SF window size registers). Clear Threshold. Reset 2 5D8
Table 199. STS-Nc Signal Fail Detect Threshold, Window Size Select 5 (R/W) Address (Hex) 400C Bit 15:14 13:0 Name SF_STSNC_DET_WIN_SEL_5 SF_STS1_DET_THRESH_5 Description Window Size Select (chooses one of four SF window size registers). Detect Threshold. Reset 2 55E
Table 200. STS-Nc Signal Fail Clear Threshold, Window Size Select 5 (R/W) Address (Hex) 400D Bit 15:14 13:0 Name SF_STSNC_CLR_WIN_SEL_5 SF_STS1_CLR_THRESH_5 Description Window Size Select (chooses one of four SF window size registers). Clear Threshold. Reset 3 618
Table 201. STS-Nc Signal Fail Detect Threshold, Window Size Select 6 (R/W) Address (Hex) 400E Bit 15:14 13:0 Name SF_STSNC_DET_WIN_SEL_6 SF_STS1_DET_THRESH_6 Description Window Size Select (chooses one of four SF window size registers). Detect Threshold. Reset 1 51D
Table 202. STS-Nc Signal Fail Clear Threshold, Window Size Select 6 (R/W) Address (Hex) 400F Bit 15:14 13:0 Name SF_STSNC_CLR_WIN_SEL_6 SF_STS1_CLR_THRESH_6 Description Window Size Select (chooses one of four SF window size registers). Clear Threshold. Reset 2 B08
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 203. STS-Nc Signal Fail Detect Threshold, Window Size Select 7 (R/W) Address (Hex) 4010 Bit 15:14 13:0 Name SF_STSNC_DET_WIN_SEL_7 SF_STS1_DET_THRESH_7 Description Window Size Select (chooses one of four SF window size registers). Detect Threshold. Reset 2 A62
Table 204. STS-Nc Signal Fail Clear Threshold, Window Size Select 7 (R/W) Address (Hex) 4011 Bit 15:14 13:0 Name SF_STSNC_CLR_WIN_SEL_7 SF_STS1_CLR_THRESH_7 Description Window Size Select (chooses one of four SF window size registers). Clear Threshold. Reset 3 BFC
Table 205. Signal Fail Window Size 0 (R/W) Address (Hex) 4012 Bit 15:0 Name SF_WIN_SIZE_0 Description Signal Fail Window Size (in 0.5 ms increments). Reset A
Table 206. Signal Fail Window Size 1 (R/W) Address (Hex) 4013 Bit 15:0 Name SF_WIN_SIZE_1 Description Signal Fail Window Size (in 0.5 ms increments). Reset 64
Table 207. Signal Fail Window Size 2 (R/W) Address (Hex) 4014 Bit 15:0 Name SF_WIN_SIZE_2 Description Signal Fail Window Size (in 0.5 ms increments). Reset 3E8
Table 208. Signal Fail Window Size 3 (R/W) Address (Hex) 4015 Bit 15:0 Name SF_WIN_SIZE_3 Description Signal Fail Window Size (in 0.5 ms increments). Reset 2710
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Data Sheet May 2003
Microprocessor Interface (continued)
STS-192 Level Path Trace Registers
s
Base address: 0x4100
The operation of the path trace registers is identical to the operation of the section trace registers. Refer to the section trace registers for a description on how to use the path trace registers. Table 209. Path Trace Access Control (R/W) Address (Hex) 4100 Bit 15:4 3:2 Name -- CH_SEL Description Unused. Program to zero. STS-48 Channel Select for J1. 3 = Channel 4. 2 = Channel 3. 1 = Channel 2. 0 = Channel 1. J1 Buffer Message Type Select. 1 = Compare value. 0 = Received message. J1 Buffer Access Mode. 1 = Write. 0 = Read. Reset 0 0
1
BUF_MSG_SEL
0
0
BUF_RNW
0
Table 210. Path Trace Access Complete Status (W1C) Address (Hex) 4101 Bit 15:1 0 Name -- J1_AXS_DONE Description Unused. May write ones on clear (W1C) if desired. J1 Access Done. Reset 0 0
Table 211. Path Trace Access Start Address (Hex) 4102 Bit 15:1 0 Name -- J1_AXS_START Description Unused. May write ones on clear (W1C) if desired. Begin J1 Access. Reset 0 0
Table 212. Path Trace Buffer Word #1--Word #32 Address (Hex) 4110--412F Bit 15:0 Name J1_UP_BUFFERn Description Path Trace Bytes. Reset 0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
STS-48 Level POH Registers
s s
Base address: 0x4400 STS-48 channel offset: 0x0100
Table 213. STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (RO) Address (Hex) 4400 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CH_ISR_BIT15 CH_ISR_BIT14 CH_ISR_BIT13 CH_ISR_BIT12 CH_ISR_BIT11 CH_ISR_BIT10 CH_ISR_BIT9 CH_ISR_BIT8 CH_ISR_BIT7 CH_ISR_BIT6 CH_ISR_BIT5 CH_ISR_BIT4 CH_ISR_BIT3 CH_ISR_BIT2 CH_ISR_BIT1 CH_ISR_BIT0 Description STS-1 #16 Interrupt Alarm. STS-1 #15 Interrupt Alarm. STS-1 #14 Interrupt Alarm. STS-1 #13 Interrupt Alarm. STS-1 #12 Interrupt Alarm. STS-1 #11 Interrupt Alarm. STS-1 #10 Interrupt Alarm. STS-1 #9 Interrupt Alarm. STS-1 #8 Interrupt Alarm. STS-1 #7 Interrupt Alarm. STS-1 #6 Interrupt Alarm. STS-1 #5 Interrupt Alarm. STS-1 #4 Interrupt Alarm. STS-1 #3 Interrupt Alarm. STS-1 #2 Interrupt Alarm. STS-1 #1 Interrupt Alarm. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) Address (Hex) 4401 Bit 15 Name CH_ISR_BIT15_M Description STS-1 #16 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #15 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #14 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #13 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #12 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
14
CH_ISR_BIT14_M
0
13
CH_ISR_BIT13_M
0
12
CH_ISR_BIT12_M
0
11
CH_ISR_BIT11_M
0
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Data Sheet May 2003
Microprocessor Interface (continued)
Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) (continued) Address (Hex) 4401 Bit 10 Name CH_ISR_BIT10_M Description STS-1 #11 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #10 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #9 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #8 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #7 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #6 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #5 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #4 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #3 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #2 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #1 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
9
CH_ISR_BIT9_M
0
8
CH_ISR_BIT8_M
0
7
CH_ISR_BIT7_M
0
6
CH_ISR_BIT6_M
0
5
CH_ISR_BIT5_M
0
4
CH_ISR_BIT4_M
0
3
CH_ISR_BIT3_M
0
2
CH_ISR_BIT2_M
0
1
CH_ISR_BIT1_M
0
0
CH_ISR_BIT0_M
0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 215. STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (RO) Address (Hex) 4402 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CH_ISR_BIT15 CH_ISR_BIT14 CH_ISR_BIT13 CH_ISR_BIT12 CH_ISR_BIT11 CH_ISR_BIT10 CH_ISR_BIT9 CH_ISR_BIT8 CH_ISR_BIT7 CH_ISR_BIT6 CH_ISR_BIT5 CH_ISR_BIT4 CH_ISR_BIT3 CH_ISR_BIT2 CH_ISR_BIT1 CH_ISR_BIT0 Description STS-1 #32 Interrupt Alarm. STS-1 #31 Interrupt Alarm. STS-1 #30 Interrupt Alarm. STS-1 #29 Interrupt Alarm. STS-1 #28 Interrupt Alarm. STS-1 #27 Interrupt Alarm. STS-1 #26 Interrupt Alarm. STS-1 #25 Interrupt Alarm. STS-1 #24 Interrupt Alarm. STS-1 #23 Interrupt Alarm. STS-1 #22 Interrupt Alarm. STS-1 #21 Interrupt Alarm. STS-1 #20 Interrupt Alarm. STS-1 #19 Interrupt Alarm. STS-1 #18 Interrupt Alarm. STS-1 #17 Interrupt Alarm. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Data Sheet May 2003
Microprocessor Interface (continued)
Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) Address (Hex) 4403 Bit 15 Name CH_ISR_BIT15_M Description STS-1 #32 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #31 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #30 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #29 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #28 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #27 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #26 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #25 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #24 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #23 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #22 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
14
CH_ISR_BIT14_M
0
13
CH_ISR_BIT13_M
0
12
CH_ISR_BIT12_M
0
11
CH_ISR_BIT11_M
0
10
CH_ISR_BIT10_M
0
9
CH_ISR_BIT9_M
0
8
CH_ISR_BIT8_M
0
7
CH_ISR_BIT7_M
0
6
CH_ISR_BIT6_M
0
5
CH_ISR_BIT5_M
0
158
Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) (continued) Address (Hex) 4403 Bit 4 Name CH_ISR_BIT4_M Description STS-1 #21 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #20 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #19 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #18 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #17 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
3
CH_ISR_BIT3_M
0
2
CH_ISR_BIT2_M
0
1
CH_ISR_BIT1_M
0
0
CH_ISR_BIT0_M
0
Table 217. STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (RO) Address (Hex) 4404 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CH_ISR_BIT15 CH_ISR_BIT14 CH_ISR_BIT13 CH_ISR_BIT12 CH_ISR_BIT11 CH_ISR_BIT10 CH_ISR_BIT9 CH_ISR_BIT8 CH_ISR_BIT7 CH_ISR_BIT6 CH_ISR_BIT5 CH_ISR_BIT4 CH_ISR_BIT3 CH_ISR_BIT2 CH_ISR_BIT1 CH_ISR_BIT0 Description STS-1 #48 Interrupt Alarm. STS-1 #47 Interrupt Alarm. STS-1 #46 Interrupt Alarm. STS-1 #45 Interrupt Alarm. STS-1 #44 Interrupt Alarm. STS-1 #43 Interrupt Alarm. STS-1 #42 Interrupt Alarm. STS-1 #41 Interrupt Alarm. STS-1 #40 Interrupt Alarm. STS-1 #39 Interrupt Alarm. STS-1 #38 Interrupt Alarm. STS-1 #37 Interrupt Alarm. STS-1 #36 Interrupt Alarm. STS-1 #35 Interrupt Alarm. STS-1 #34 Interrupt Alarm. STS-1 #33 Interrupt Alarm. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) Address (Hex) 4405 Bit 15 Name CH_ISR_BIT15_M Description STS-1 #48 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #47 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #46 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #45 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #44 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #43 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #42 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #41 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #40 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #39 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #38 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #37 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #36 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #35 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
14
CH_ISR_BIT14_M
0
13
CH_ISR_BIT13_M
0
12
CH_ISR_BIT12_M
0
11
CH_ISR_BIT11_M
0
10
CH_ISR_BIT10_M
0
9
CH_ISR_BIT9_M
0
8
CH_ISR_BIT8_M
0
7
CH_ISR_BIT7_M
0
6
CH_ISR_BIT6_M
0
5
CH_ISR_BIT5_M
0
4
CH_ISR_BIT4_M
0
3
CH_ISR_BIT3_M
0
2
CH_ISR_BIT2_M
0
160
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) (continued) Address (Hex) 4405 Bit 1 Name CH_ISR_BIT1_M Description STS-1 #34 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. STS-1 #33 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0
0
CH_ISR_BIT0_M
0
Table 219. STS-48 Channel Path Trace Control (R/W) Address (Hex) 4406 Bit 15:10 9 Name -- MODE_SEL Description Unused. Program to zero. J1 Message Mode Select. 1 = Validated mode. 0 = Provisioned mode. J1 Message Type Select. 1 = SDH. 0 = SONET. Unused. Program to zero. STS-1 # Select for J1 Accumulation (1--48; other values disable the feature). Reset 0 0
8
TYPE_SEL
0
7:6 5:0
-- STS48_CH_J1_STS_SEL
0 0
Table 220. S/W Concatenation Map STS-1 #1 to STS-1 #12 (R/W) Address (Hex) 4407 Bit 15:12 11 10:0 Name -- SW_CONC_MAP_STS12 SW_CONC_MAP_STS11-- SW_CONC_MAP_STS1 Description Unused. Program to zero. STS-1 #12 Concatenation Map Bit. STS-1 #11 to STS-1 #1 Concatenation Map Bits. Reset 0 0 0
Table 221. S/W Concatenation Map STS-1 #13 to STS-1 #24 (R/W) Address (Hex) 4408 Bit 15:12 11 10:0 Name -- SW_CONC_MAP_STS24 SW_CONC_MAP_STS23-- SW_CONC_MAP_STS13 Description Unused. Program to zero. STS-1 #24 Concatenation Map Bit. STS-1 #23 to STS-1 #13 Concatenation Map Bits. Reset 0 0 0
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Data Sheet May 2003
Microprocessor Interface (continued)
Table 222. S/W Concatenation Map STS-1 #25 to STS-1 #36 (R/W) Address (Hex) 4409 Bit 15:12 11 10:0 Name -- SW_CONC_MAP_STS36 SW_CONC_MAP_STS35-- SW_CONC_MAP_STS25 Description Unused. Program to zero. STS-1 #36 Concatenation Map Bit. STS-1 #35 to STS-1 #25 Concatenation Map Bits. Reset 0 0 0
Table 223. S/W Concatenation Map STS-1 #37 to STS-1 #48 (R/W) Address (Hex) 440A Bit 15:12 11 10:0 Name -- SW_CONC_MAP_STS48 SW_CONC_MAP_STS47-- SW_CONC_MAP_STS37 Description Unused. Program to zero. STS-1 #48 Concatenation Map Bit. STS-1 #47 to STS-1 #37 Concatenation Map Bits. Reset 0 0 0
Table 224. S/W Concatenation Mask STS-1 #1 to STS-1 #12 (R/W) Address (Hex) 440B Bit 15:12 11 10:0 Name -- SW_CONC_MASK_STS12 SW_CONC_MASK_STS11-- SW_CONC_MASK_STS1 Description Unused. Program to zero. STS-1 #12 Concatenation Mask Bit. STS-1 #11 to STS-1 #1 Concatenation Mask Bits. Reset 0 0 0
Table 225. S/W Concatenation Mask STS-1 #13 to STS-1 #24 (R/W) Address (Hex) 440C Bit 15:12 11 10:0 Name -- SW_CONC_MASK_STS24 SW_CONC_MASK_STS23-- SW_CONC_MASK_STS13 Description Unused. Program to zero. STS-1 #24 Concatenation Mask Bit. STS-1 #23 to STS-1 #13 Concatenation Mask Bits. Reset 0 0 0
Table 226. S/W Concatenation Mask STS-1 #25 to STS-1 #36 (R/W) Address (Hex) 440D Bit 15:12 11 10:0 Name -- SW_CONC_MASK_STS36 SW_CONC_MASK_STS35-- SW_CONC_MASK_STS25 Description Unused. Program to zero. STS-1 #36 Concatenation Mask Bit. STS-1 #35 to STS-1 #25 Concatenation Mask Bits. Reset 0 0 0
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 227. S/W Concatenation Mask STS-1 #37 to STS-1 #48 (R/W) Address (Hex) 440E Bit 15:12 11 10:0 Name -- SW_CONC_MASK_STS48 SW_CONC_MASK_STS47-- SW_CONC_MASK_STS37 Description Unused. Program to zero. STS-1 #48 Concatenation Mask Bit. STS-1 #47 to STS-1 #37 Concatenation Mask Bits. Reset 0 0 0
Table 228. Received Concatenation Map STS-1 #1 to STS-1 #12 (RO) Address (Hex) 440F Bit 15:12 11 10:0 Name -- RECD_CONC_MAP_STS12 Description Reset 0 0 0
Unused. Program to zero. STS-1 #12 Received Concatenation Map Bit. RECD_CONC_MAP_STS11-- STS-1 #11 to STS-1 #1 Received ConcateRECD_CONC_MAP_STS1 nation Map Bits.
Table 229. Received Concatenation Map STS-1 #13 to STS-1 #24 (RO) Address (Hex) 4410 Bit 15:12 11 10:0 Name -- RECD_CONC_MAP_STS24 Description Reset 0 0 0
Unused. Program to zero. STS-1 #24 Received Concatenation Map Bit. RECD_CONC_MAP_STS23-- STS-1 #23 to STS-1 #13 Received ConcateRECD_CONC_MAP_STS13 nation Map Bits.
Table 230. Received Concatenation Map STS-1 #25 to STS-1 #36 (RO) Address (Hex) 4411 Bit 15:12 11 10:0 Name -- RECD_CONC_MAP_STS36 Description Reset 0 0 0
Unused. Program to zero. STS-1 #36 Received Concatenation Map Bit. RECD_CONC_MAP_STS35-- STS-1 #35 to STS-1 #25 Received ConcateRECD_CONC_MAP_STS25 nation Map Bits.
Table 231. Received Concatenation Map STS-1 #37 to STS-1 #48 (RO) Address (Hex) 4412 Bit 15:12 11 10:0 Name -- RECD_CONC_MAP_STS48 Description Reset 0 0 0
Unused. Program to zero. STS-1 #48 Received Concatenation Map Bit. RECD_CONC_MAP_STS47-- STS-1 #47 to STS-1 #37 Received ConcateRECD_CONC_MAP_STS37 nation Map Bits.
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Data Sheet May 2003
Microprocessor Interface (continued)
Table 232. STS-48 Channel Path Alarms 1 (W1C) Address (Hex) 4413 Bit 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Name -- CONC_MAP_MMCH_4 CONC_MAP_MMCH_3 CONC_MAP_MMCH_2 CONC_MAP_MMCH_1 UNSUPP_CONC_MAP_4 UNSUPP_CONC_MAP_3 UNSUPP_CONC_MAP_2 UNSUPP_CONC_MAP_1 -- J1_BUF_PAR_ERR J1_NEW_MSG J1_MSG_MMCH Description Unused. May write ones on clear (W1C) if desired. Concatenation Map Mismatch in STS-1 #37--STS-1 #48. Concatenation Map Mismatch in STS-1 #25--STS-1 #36. Concatenation Map Mismatch in STS-1 #13--STS-1 #24. Concatenation Map Mismatch in STS-1 #1--STS-1 #12. Unsupported Concatenation in STS-1 #37-- STS-1 #48. Unsupported Concatenation in STS-1 #25-- STS-1 #36. Unsupported Concatenation in STS-1 #13-- STS-1 #24. Unsupported Concatenation in STS-1 #1-- STS-1 #12. Unused. May write ones on clear (W1C) if desired. J1 Memory Parity Error. J1 New Validated Message. J1 Message Mismatch. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
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Agere Systems Inc.
Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Microprocessor Interface (continued)
Table 233. STS-48 Channel Path Alarms 1 Mask (W1C) Address (Hex) 4414 Bit 15:12 11 Name -- CONC_MAP_MMCH_4_M Description Unused. May write ones on clear (W1C) if desired. Concatenation Map Mismatch in STS-1 #37--STS-1 #48 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Concatenation Map Mismatch in STS-1 #25--STS-1 #36 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Concatenation Map Mismatch in STS-1 #13--STS-1 #24 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Concatenation Map Mismatch in STS-1 #1--STS-1 #12 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unsupported Concatenation in STS-1 #37-- STS-1 #48 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unsupported Concatenation in STS-1 #25-- STS-1 #36 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unsupported Concatenation in STS-1 #13-- STS-1 #24 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unsupported Concatenation in STS-1 #1-- STS-1 #12 Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Unused. May write ones on clear (W1C) if desired. J1 Memory Parity Error Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. J1 New Validated Message Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. J1 Message Mismatch Interrupt Mask. 1 = Enable interrupt. 0 = Mask interrupt. Reset 0 0
10
CONC_MAP_MMCH_3_M
0
9
CONC_MAP_MMCH_2_M
0
8
CONC_MAP_MMCH_1_M
0
7
UNSUPP_CONC_MAP_4_M
0
6
UNSUPP_CONC_MAP_3_M
0
5
UNSUPP_CONC_MAP_2_M
0
4
UNSUPP_CONC_MAP_1_M
0
3 2
-- J1_BUF_PAR_ERR_M
0 0
1
J1_NEW_MSG_M
0
0
J1_MSG_MMCH_M
0
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Data Sheet May 2003
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this device specification. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 234. Absolute Maximum Ratings Parameter dc Supply Voltage: 3.3 V Power 2.5 V Power Analog Power Storage Temperature Maximum Power Dissipation: 3.3 V Power Supply 2.5 V Power Supply Symbol VDD VDD2 VDDA Tstg PD3 PD2 Min -0.5 -0.5 -0.5 -65 -- -- Typ 3.3 2.5 3.3 -- -- -- Max 3.8 3.0 3.8 125 6.71 3.5 Unit V V V C W W
1. The maximum power dissipation for the five analog power supply inputs is 350 mW (5 x 70 mW each). This total is included in PD3.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters. Device TSOT0410G4 Model HBM CDM (corner pins) CDM (noncorner pins) Voltage TBD TBD TBD
Recommended Operating Conditions
Table 235. Recommended Operating Conditions Parameter Junction Temperature Range Ambient Operating Temperature Range 3.3 V Power Supply 2.5 V Power Supply Analog Power Supply Symbol TJ TA VDD VDD2 VDDA Min -40 -40 3.135 2.375 3.135 Typ -- -- 3.3 2.5 3.3 Max 125 85 3.465 2.625 3.465 Unit C C V V V
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Recommended Operating Conditions (continued)
s s s
The TSOT0410G4 is packaged in a 9-layer LBGA. The heat sink is not grounded in the TSOT0410G4. The thermal resistance junction to case, JC, of the 600-pin LBGA package is 0.4 C/W. The thermal resistance junction to ambient (to the nearest 0.5 C/W), JA, of the 600-pin LBGA package is given in Table 236.
Table 236. Thermal Resistance--Junction to Ambient Air Speed in Linear Feet per Minute (LFPM) JEDEC Standard Natural Convection 0 200 500 800 JA (C/W) 9 8.5 6.5 6 5
Electrical Characteristics
Power Sequencing
The device power may be applied concurrently to both voltage level inputs. If power sequencing is used for other devices on a board or in a system, it is a preferred that the highest voltage be applied first and removed last.
Low-Voltage Differential Signal (LVDS) Buffers
The LVDS buffers are compliant with the EIA-644 standard. The only exception to compliance with this standard is associated with the input leakage current. The LVDS input buffers have an input leakage current of 300 A maximum. The LVDS buffers are also compliant to the IEEE 1596.3 standard. The only exception to compliance with this standard is the input termination resistance. The LVDS input buffers have an input termination resistance of 80 --135 . The LVDS outputs are hot-swap compatible, and can be connected to other vendor's LVDS I/O buffers. The maximum input current for the Agere LVDS input buffers is 9 mA. Prolonged exposure to higher current levels will have an impact on long-term reliability. CML or open collector transmitters cannot be directly connected to the TSOT0410G4 LVDS inputs. This is not possible, since up to four LVDS inputs share one center tap line with one center tap pin. The 10 m center tap line is relatively long in the TSOT0410G4; therefore, resistances and capacitances cannot be ignored. Unused LVDS inputs may be left unconnected. There are internal pull-up resistors (nominal 14 k) that pull open inputs to greater than 2.75 Vdc (the common mode range is 0 Vdc to 2.4 Vdc). A sense circuit becomes active for input voltages above 2.75 Vdc and clamps the buffer output to a defined state. Open inputs will not oscillate for this reason. For board layout, LVDS traces should be run on controlled-impedance layers, and should be specified as 50 line-to-ground. The LVDS buffers support point-to-point connections. They are not intended for bused implementations.
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Data Sheet May 2003
Electrical Characteristics (continued)
LVDS DRIVER LVDS RECEIVER
100
CENTER TAP
50 50
EXTERNAL DEVICE PINS
5-8703(F)
Figure 12. LVDS Driver and Receiver and Associated Internal Components
DRIVER
INTERCONNECT
RECEIVER
VOA
A
AA
VIA
VOB
B
BB
VIB
VGPD
5-8704(F)
Figure 13. LVDS Driver and Receiver
CA VOA A RLOAD VOB B CB V VOD = (VOA - VOB)
5-8705(F)
Figure 14. LVDS Driver
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Data Sheet May 2003
TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Electrical Characteristics (continued)
LVDS Receiver Buffer Capabilities A disabled or unpowered LVDS receiver can withstand a driving LVDS transmitter over the full range of driver operating range, for an unlimited period of time, without being damaged. Table 237 illustrates LVDS driver dc data, Table 238 the ac data, and Table 240 on page 170 the LVDS receiver data. Note: VDD = 3.1 V--3.5 V, 0 C--125 C, slow-fast process. Table 237. LVDS Driver dc Data Parameter Driver Output Voltage High, VOA or VOB Driver Output Voltage Low, VOA or VOB Driver Output Differential Voltage VOD = (VOA - VOB) (with external reference resistor) Driver Output Offset Voltage VOS = (VOA + VOB)/2 Output Impedance, Single-ended RO Mismatch Between A and B Change in VODBetween 0 and 1 Change in VOSBetween 0 and 1 Output Current Output Current Power-off Output Leakage Symbol VOH VOL VOD Conditions RLOAD = 100 1%. RLOAD = 100 1%. RLOAD = 100 1%. Min -- 0.9251 0.25 Typ -- -- -- Max 1.500 -- 0.451
1
Unit V V V
VOS RO " RO VOD VOS ISA, ISB ISAB IXA, IXB
RLOAD = 100 1%, 1.1251 refer to Figure 14 on page 168. VCM = 1.0 V and 1.4 V. VCM = 1.0 V and 1.4 V. RLOAD = 100 1%. RLOAD = 100 1%. Driver shorted to ground. Driver shorted together. VDD = 0 V, VPAD, VPADN = 0 V--3 V. 40 -- -- -- -- -- --
-- 50 -- -- -- -- -- --
1.2751 60 10 25 25 24 12 30
V % mV mV mA mA
A
1. External reference, REF10 = 1.0 V 3%, REF14 = 1.4 V 3%.
Table 238. LVDS Driver ac Data Parameter VOD Fall Time, 80% to 20% VOD Rise Time, 20% to 80% Differential Skew tpHLA - tpLHB ortpHLB - tpLHA Symbol tFALL tRISE tSKEW1 Conditions ZLOAD = 100 1%, CPAD = 3.0 pF, CPADN = 3.0 pF. ZLOAD = 100 1%, CPAD = 3.0 pF, CPADN = 3.0 pF. Any differential pair on package at 50% point of the transition. Min 100 100 -- Max 200 200 50 Unit ps ps ps
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Electrical Characteristics (continued)
Table 239. LVDS Driver Reference Data Parameter REF10E, REF10L Voltage Range REF14E, REF14L Voltage Range Nominal Input Current--REF10 and REF14 Reference Inputs Table 240. LVDS Receiver Data Parameter Receiver input Voltage Range, VIA or VIB (common mode voltage) Receiver Input Differential Threshold (differential mode voltage) Receiver Input Differential Hysteresis Receiver Differential Input Impedance Symbol VI VIDTH VHYST RIN Conditions VGPD< 925 mV dc--1 MHz. VGPD< 925 mV 400 MHz. VIDTHH - VIDTHL. With built-in termination, center tapped. Min 0 -100 -- 80 Typ 1.2 -- -- 100 Max 2.4 100 --1 135 Unit V mV mV Conditions -- -- -- Min 0.95 1.35 -- Typ 1.0 1.4 10 Max 1.05 1.45 -- Unit V V A
1. Buffer will not produce transition when input is open-circuited.
Table 241. Receive Payload Add Interface Parameter Input Data1 -- Over a 200 ns time -- interval.3 -- -- 0.4 -- -- -- 60 100 -- bits ps UIp-p Stream of Nontransitional 622 Mbits/s2 Phase Change, Input Signal Eye Opening4 Jitter Jitter Tolerance: 250 kHz 25 kHz 2 kHz -- -- -- -- -- -- -- -- -- 0.6 6 60 UIp-p UIp-p UIp-p Conditions Min Typ Max Unit
1. 622.08 Mbits/s scrambled data stream conforming to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence: -- PN7 characteristic is 1 + x6 + x7. -- PN9 characteristic is 1 + x4 + x9. 2. This sequence should not occur more than once per minute. 3. Translates to a frequency change of 500 ppm. 4. A unit interval for 622.08 Mbits/s data is 1.6075 ns.
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Electrical Characteristics (continued)
Table 242. Receive Payload Drop Interface Parameter Output Jitter, Generated Conditions 250 kHz to 5 MHz. Min -- Typ -- Max 0.25 Unit UIp-p
Table 243. LVTTL 3.3 V Logic Interface Characteristics Parameter Input Leakage Input Voltage: Low High Output Voltage: Low High Input Capacitance Load Capacitance Symbol IL VILLVTTL VIHLVTTL VOLLVTTL VOHLVTTL CI CL Conditions -- -- -- -5.0 mA 5.0 mA -- -- Min -- GND VDD - 1.0 GND VDD - 1.0 -- -- Typ -- -- -- -- -- 2.2 0.4 Max 1.0 1.0 VDD 0.5 VDD 3.0 -- Unit A V V V V pF pF
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Timing Characteristics
Receive Data Interface
Receive STS-48/STS-192 Data Figure 15 illustrates the timing for the receive STS-48/STS-192 data stream. Both the clock and data pins are low-voltage differential signal (LVDS) input buffers. The expected clock rate is 622.08 MHz and the receive data is clocked on the rising edge of the clock. In STS-48 mode, each channel uses one set of R_CLK_n and RD_n_[3:0] data pins. In STS-192 mode, only R_CLK_1 is used, along with the 16 RD pins. The timing values for the diagram are given in Table 244.
t1 P R_CLK N t2 N RD P t4 P R_CLKO N
5-9085(F)r.1
t3
Figure 15. Receive Data Timing Table 244. Receive Data Timing Symbol t1 t2 t3 t4 Parameter Clock Period Data Setup Time Required Data Hold Time Required R_CLK to R_CLKO Rising Edge R_CLK to R_CLKO Falling Edge Min -- 250 250 2.35 2.40 Typ 1608 -- -- -- -- Max -- -- -- 5.54 5.61 Unit ps ps ps ns ns
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Timing Characteristics (continued)
Receive Transport Overhead Interface
Figure 16 illustrates the timing for the following receive data communication channel interfaces: local orderwire (RLCLOW), express orderwire (REXPOW), section user channel (RSUSER), section data com (RSDCC), and line data com (RLDCC). Figure 16 is also appropriate to illustrate the timing for the transmit add section data com channel (TADCC and TADCK). Table 258 on page 183 also references this figure.
t10 t11 DCC CLOCK PIN
t12 DCC DATA PIN
5-9087(F)
Figure 16. Receive Data Communication Channels Timing Receive Local Orderwire The receive local orderwire (RLCLOW) pin is timed using the rising edge of the receive orderwire clock (ROW_CLK) pin. Sampling of the RLCLOW pin is intended to occur at the negative edge of ROW_CLK signal. The frequency of ROWCK is 64 kHz with a duty cycle of 33%. The timing characteristics for these pins are given in Table 245 on page 174. Receive Section User The receive section user (RSUSER) pin is timed using the rising edge of the receive orderwire clock (ROW_CLK) pin. Sampling of the RSUSER pin is intended to occur at the negative edge of ROW_CLK signal. The timing characteristics for these pins are given in Table 245.
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Timing Characteristics (continued)
Receive Express Orderwire The receive express orderwire (REXPOW) pin is timed using the rising edge of the receive orderwire clock (ROW_CLK) pin. Sampling of the REXPOW pin is intended to occur at the negative edge of ROW_CLK signal. The timing characteristics for these pins are given in Table 245. Table 245. RLCLOW/RSUSER/REXPOW Timing Symbol t10 t11 t12 Parameter Clock Period Clock High Width Clock to Data Delay Min -- -- -- Typ 15.625 5.21 30 Max -- -- -- Unit s s ns
Receive Section Data Com The receive section data com (RSDCC) pin is timed using the rising edge of the receive section data com clock (RSDCK) pin. Sampling of the RSDCC pin is intended to occur at the negative edge of RSD_CLK signal. The frequency of RSD_CLK is 192 kHz with a duty cycle of 33%. The timing characteristics for these pins are given in Table 246. (See Figure 16 on page 173.) Table 246. RSDCC Timing Symbol t10 t11 t12 Parameter Clock Period Clock High Width Clock to Data Delay Min -- -- -- Typ 5.208 1.736 30 Max -- -- -- Unit s s ns
Receive Line Data Com The receive line data com (RLDCC) pin is timed using the rising edge of the receive line data com clock (RLD_CLK) pin. Sampling of the RLDCC pin is intended to occur at the negative edge of RLD_CLK signal. The frequency of RLD_CLK is 576 kHz with a duty cycle of roughly 50%. The timing characteristics for these pins are given in Table 247. (See Figure 16 on page 173.) Table 247. RLDCC Timing Symbol t10 t11 t12 Parameter Clock Period Clock High Width Clock to Data Delay Min -- -- -- Typ 1.736 0.823 30 Max -- -- -- Unit s s ns
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Timing Characteristics (continued)
Receive Overhead Serial Link The ROHDAT_n_[1:0] pins transmit the complete transport overhead data for every received frame. The ROHDAT_n_ [1:0] pins are timed using the rising edge of the ROH_CLK signal. Sampling of the ROHDAT_n_[1:0] pins is intended to occur at the positive edge of the ROH_CLK signal. Since 1296 overhead bytes are transmitted in 125 s using a 2-bit interface, the average frequency of ROH_CLK is 41.472 MHz. Internally, this clock is produced using a 155.52 MHz reference, which requires a divide-down factor of 3.75. This is accomplished by producing three 38.88 MHz clock cycles (long clocks), followed by one 51.84 MHz clock cycle (short clock). The ROHFP pin indicates the frame position by toggling high during the most significant bit of the first A1 byte in the data stream, as illustrated in Figure 17. External logic that interfaces to ROHDAT should synchronize to each of the four channels independently using the ROHFP_[1--4] signals. Even in 10 Gbits/s mode, where RXCLK and ROHCLK are the same, the different delays on the signals in each channel will create the potential for the metastability handlers to sample the channels, within 1 clock cycles, of each other. This is due to the possibility of the four channels being asynchronous. The timing characteristics for the receive overhead serial pins are given in Table 248.
t13 t14 ROH_CLK[4--1]
t15 t14
t16 ROHDAT_[4--1]_[1:0] E2... A1 [7:6] MSB t17 ROHFP_[4--1] A1 [5:4] A1 [3:2] A1 [1:0] LSB A1 ...
5-9088.e (F)
Figure 17. Receive Overhead Serial Timing Table 248. Receive Overhead Serial Timing Symbol t13 t14 t15 t16 t17 Parameter Clock Period (long clock) Clock High Width Clock Period (short clock) Clock to Data Delay Clock to Frame Pulse Delay Min -- 12.8 -- 0.9 0.6 Typ 25.6 12.9 19.2 -- -- Max -- 13.3 -- 8 7 Unit ns ns ns ns ns 175
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Data Sheet May 2003
Timing Characteristics (continued)
Transmit Data Interface
Transmit STS-48/STS-192 Data Figure 18 illustrates the timing for the transmit STS-48/STS-192 data stream. Both the clock and data pins are driven with low-voltage differential signal buffers. T_CLK, being a 622.08 MHz input clock, starts at the transmit add interface and clocks out the transmit data on the negative edge. The clock is then output on the T_CLKO_N pin. The timing values for the diagram are given in Table 249.
t23 N T_CLK P t18 N T_CLKO P t19 t20 P TD N t21 t22
5-9089(F)r.2
Figure 18. Transmit Data Timing Table 249. Transmit Data Timing Symbol t18 t19 t20 t21 t22 t23 Parameter Clock Period Data Delay from Clock Edge Data Uncertainty Data Rise Time: 20%--80% Data Fall Time: 80%--20% Clock In to Clock Out Min -- -50 -- 100 100 2400 Typ 1608 -- -- -- -- Max -- 250 200 200 200 4600 Unit ps ps ps ps ps ps
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Timing Characteristics (continued)
Transmit Frame Figure 19 illustrates the timing for the transmit frame (TFRM) signal, which is sampled using a high-speed, low-voltage differential input buffer on the positive edge of T_CLK. The timing values are given in Table 250.
P T_CLK N
t24
t25 N TFRM P
t26
5-9090(F)
Figure 19. Transmit Frame Timing Table 250. Transmit Frame Timing Symbol t24 t25 t26 Parameter Clock Period Data Setup Time Required Data Hold Time Required Min -- 300 300 Typ 1608 -- -- Max -- -- -- Unit ps ps ps
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Timing Characteristics (continued)
Transmit Transport Overhead Interface
Figure 20 illustrates the timing for the following transmit data communication channel interfaces: local orderwire (TLCLOW), express orderwire (TEXPOW), section user channel (TSUSER), section data com (TSDCC), and line data com (TLDCC).
t27 t28 DCC CLOCK PIN
t29 DCC DATA PIN
t30
5-9091(F)
Figure 20. Transmit Data Communication Channels Timing Transmit Local Orderwire The transmit local orderwire (TLCLOW) pin is clocked in using the rising edge of the transmit orderwire clock (TOW_CLK) pin. Generation of the signal feeding the TLCLOW_n pin is intended to occur at the negative edge of TOW_CLK signal. This clock signal, running at 64 kHz, is an output of the device. The timing characteristics for these pins are given in Table 251. Table 251. TLCLOW/TSUSER/TEXPOW Timing Symbol t27 t28 t29 t30 Parameter Clock Period Clock High Width Data Setup Time Required Data Hold Time Required Min -- -- -- -- Typ 15.625 5.21 30 0 Max -- -- -- -- Unit s s ns ns
Transmit Section User The transmit section user (TSUSER) pin is clocked in using the rising edge of the transmit orderwire clock (TOW_CLK) pin. Generation of the signal feeding the TSUSER pin is intended to occur at the negative edge of TOW_CLK signal. The timing characteristics for these pins are given in Table 251. Transmit Express Orderwire The transmit express orderwire (TEXPOW) pin is clocked in using the rising edge of the transmit orderwire clock (TOW_CLK) pin. Generation of the signal feeding the TEXPOW pin is intended to occur at the negative edge of TOW_CLK signal. The timing characteristics for these pins are given in Table 251.
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Timing Characteristics (continued)
Transmit Section Data Com The transmit section data com (TSDCC) pin is clocked in using the rising edge of the transmit section data com clock (TSD_CLK) pin. Generation of the signal feeding the TSDCC pin is intended to occur at the negative edge of TSD_CLK signal. This clock signal, running at 192 kHz, is an output of the device. The timing characteristics for these pins are given in Table 252. (See Figure 20 on page 178.) Table 252. TSDCC Timing Symbol t27 t28 t29 t30 Parameter Clock Period Clock High Width Data Setup Time Required Data Hold Time Required Min -- -- -- -- Typ 5.208 1.736 30 0 Max -- -- -- -- Unit s s ns ns
Transmit Line Data Com The transmit line data com (TLDCC) pin is clocked in using the rising edge of the transmit line data com clock (TLD_CLK) pin. Generation of the signal feeding the TLDCC pin is intended to occur at the negative edge of TLD_CLK signal. This clock signal, running at 576 kHz, is an output of the device. The timing characteristics for these pins are given in Table 253. (See Figure 20 on page 178.) Table 253. TLDCC Timing Symbol t27 t28 t29 t30 Parameter Clock Period Clock High Width Data Setup Time Required Data Hold Time Required Min -- -- -- -- Typ 1.736 0.823 30 0 Max -- -- -- -- Unit s s ns ns
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Timing Characteristics (continued)
Transmit Overhead Serial Link
t31 t32 TOH_CLK t35 t34 TOHDAT_[1:0] ... E2 A1 [7:6] MSB t38 TOHFP A1 [5:4]
t33 t32
A1 [3:2]
A1 [1:0] LSB
A1...
t37 t36 TOHEN
5-9092(F)
Figure 21. Transmit Overhead Serial Timing The TOHDAT_n_[1:0] pins are optionally used to insert transport overhead bytes into the transmit data stream. The TOHDAT_n_[1:0] pins are sampled internally using the rising edge of the TOH_CLK signal. Generation of the TOHDAT signal is intended to occur at the positive edge of the TOH_CLK signal. This is possible since there is zero hold time required on the TOHDAT inputs. All of the TOH inputs/outputs are synchronous. Internal to TSOT, one TOH clock is generated and routed to all four TOH_CLK_n pins. The TOH_CLK outputs are redundant copies, and only one has to be used if the TOH_DAT signals are brought to a common device, such as an FPGA. (There will not be any phase jumps between the outputs.) The skew between the four TOH_CLK outputs is 1 ns maximum. Since 1296 overhead bytes are received in 125 s using a 2-bit interface, the average frequency of TOH_CLK is 41.472 MHz. Internally, this clock is produced using a 155.52 MHz reference, which requires a divide-down factor of 3.75. This is accomplished by producing three 38.88 MHz clock cycles (long clocks), followed by one 51.84 MHz clock cycle (short clock). The TOHFP pin indicates the frame position by toggling high during the most significant bit of the first A1 byte in the data stream, as illustrated in Figure 21. Only one TOHFP frame pulse signal is generated inside the TSOT0410G4, and it is routed to all four TOHFP_n pins. The TOHFP_n signals are all aligned. Only one is needed if the TOH_DAT signals are brought to a common device, such as an FPGA. The timing characteristics for the transmit overhead serial pins are given in Table 254 on page 181. TOHEN is only sampled on the rising edge of the clock during the least significant bit(s) of the byte; however, it can be generated for the entire byte time (as indicated by dashed line waveforms in Figure 21). 180 Agere Systems Inc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Timing Characteristics (continued)
Table 254. Transmit Overhead Serial Timing Symbol t31 t32 t33 t34 t35 t36 t37 t38 Parameter Clock Period (long clock) Clock Low Width Clock Period (short clock) Data Setup Time Required Data Hold Time Required TOHEN Setup Time Required TOHEN Hold Time Required Clock to Frame Pulse Delay1 Min -- 10.0 -- 8.0 0 8.5 0 0 Typ 25.7 12.9 19.2 -- -- -- -- -- Max -- 14.0 -- -- -- -- -- 7.0 Unit ns ns ns ns ns ns ns ns
1. The frame pulse may occur after either a long clock or a short clock.
Receive Drop Interface
Drop Clock, Drop Frame, and Drop Data The drop clock (D_CLK) and drop frame (DFRM) pins are driven using bidirectional TTL buffers. If the pointer processor is bypassed, the receive clock and receive frame are used for the drop interface and are output on the D_CLK and DFRM pins.
t5 N D_CLK P t6 N DFRM P
5-9086(F)
Figure 22. Receive Frame Timing (Pointer Processor Bypassed) Table 255. Drop Frame Timing (Pointer Processor Bypassed) Symbol t5 t6 Parameter Clock Period DFRM Delay from Clock Edge Min -- 0.3 Typ 12.86 -- Max -- 1.97 Unit ns ns
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Timing Characteristics (continued)
If the pointer processor is not bypassed, D_CLK and DFRM are inputs to the device and are used to clock out the drop data. The drop clock signal has a frequency of 77.76 MHz, which is multiplexed/divided internally to provide a 622.08 MHz clock for the drop data signals.
t5 N D_CLK P t6 N DFRM P t7
5-9086.a (F)
Figure 23. Receive Frame Timing (Pointer Processor Active) Table 256. Drop Frame Timing (Pointer Processor Active) Symbol t5 t6 t7 Parameter Clock Period DFRM Setup Time DFRM Hold Time Required Min -- 0 3 Typ 12.86 -- -- Max -- -- -- Unit ns ns ns
Receive Drop Section Data Com The receive drop data com (RDDCC) input is provided to allow the D1, D2, and D3 to be used for data transmission across a backplane, or between devices. Since the section TOH (RSOH) has been previously terminated, these bytes are no longer used and are available. Use of this input is optional. There is a corresponding output on the add interface, the TADCC. These outputs would output a similar, proprietary DCC message from another device, or across a backplane. The receive drop data com (RDDCC) pin is clocked in using the rising edge of the receive drop section data com clock (RDDCK) pin. Generation of the signal feeding the RDDCC pin is intended to occur at the negative edge of RDDCK signal. This clock signal, running at 192 kHz, is an output of the device. In reference to Figure 20 on page 178, the timing characteristics for these pins are given in Table 257. Table 257. RDDCC Timing Symbol t27 t28 t29 t30 Parameter Clock Period Clock High Width Data Setup Time Required Data Hold Time Required Min -- 2.594 30 -- Typ 5.208 -- -- 0 Max -- 2.714 -- -- Unit s s ns ns
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Timing Characteristics (continued)
Transmit Add Interface
Transmit Add Data The transmit add pins, ADATA[16:1], are asynchronous inputs to the device, and while they do not have a phase relationship to a clock, they are expected to have the same frequency as T_CLK (622.08 MHz). Furthermore, the transmit add signals for a STS-48/STS-192 channel are expected to be aligned within 75 ns of each other. Transmit Add Section Data Com The transmit add data com (TADCC) output is provided to allow the D1, D2, and D3 to be used for data transmission across a backplane, or between devices. Since the section TOH (RSOH) has not yet been formed and path is being input at the add interface, these bytes are available. Use of this output is optional. There is a corresponding input on the add interface, the RDDCC. These inputs would be used to send a similar, proprietary DCC message to another device, or across a backplane. The transmit add section data com (TADCC) pins are timed using the rising edge of the transmit add section data com clock (TADCK) pin. The data is clocked out at the rising edge of TADCK, and the TADCC pins should be read at the negative edge of TADCK signal. The timing characteristics for these pins are given in Table 258. (See Figure 16 on page 173.) Table 258. TADCC Timing Symbol t10 t11 t12 Parameter Clock Period Clock High Width Clock to Data Delay Min -- 2.594 30 Typ 5.208 -- -- Max -- 2.714 -- Unit s s ns
Microprocessor Interface Timing
Synchronous Mode The synchronous microprocessor interface mode is selected when MPMODE = 1. Interface timing for the synchronous mode write cycle is given in Figure 24 on page 184 and in Table 260 on page 184. Interface timing for the read cycle is given in Figure 25 on page 185 and in Table 262 on page 185. The parity bits, PARITY_1 and PARITY_0, are optional and may be left unconnected if not used. If unused, TEA_N should be ignored on a synchronous write.
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Timing Characteristics (continued)
In synchronous mode, a transfer error (TA_N = 1, TEA_N = 0) will occur if the internal cycle is not terminated in 32 PCLK cycles from the first rising edge of PCLK, where CS_N = 0 and TS_N = 0.
INSERTED WAITSTATES
tc PCLK CS_N t39 TS_N RW_N t40 ADDRESS_[15:0] DATA_[15:0]/PARITY_[1:0] (INPUT) TA_N/TEA_N HIGH Z
tcycle
t41 t45 HIGH Z
5-9093(F)
t42
t43
t44
Figure 24. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1) Table 259. TA_N/TEA_N Cycle Termination for Synchronous Write Cycle TA_N 0 0 1 1 TEA_N 0 1 0 1 Encoding Description Write data parity error. Normal cycle termination. Access to undefined address region--transfer error. No cycle termination--processor generated time-out.
Table 260. Microprocessor Interface Synchronous Write Cycle Specifications Symbol tc tcycle t39 t40 t41 t42 t43 t44 t45 Parameter PCLK Period Bus Transfer Cycle Time CS_N, TS_N, RW_N Valid to PCLK ADDRESS, DATA Valid to PCLK CS_N, TS_N, RW_N, ADDRESS, DATA Hold PCLK to TA_N/TEA_N 3-State to High PCLK to TA_N/TEA_N High to Low PCLK to TA_N/TEA_N Low to High PCLK to TA_N/TEA_N 3-State Min 20 8 4 18 2 3.5 5.5 5 -- Max -- 12 -- -- -- 13.5 15 13.5 4 Unit ns tc ns ns ns ns ns ns ns
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Timing Characteristics (continued)
INSERTED WAITSTATES
tcycle PCLK CS_N t39 TS_N
t47 RW_N t40 ADDRESS_[15:0] DATA_[15:0]/PARITY_[1:0] (OUTPUT) TA_N/TEA_N HIGH Z t42 t41 t46 t47 t45 HIGH Z
5-9094(F)
t44
Figure 25. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) Table 261. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle TA_N 0 0 1 1 TEA_N 0 1 0 1 Encoding Description Not possible during read cycle. Normal cycle termination. Access to undefined address region--transfer error. No cycle termination--processor generated time-out.
Table 262. Microprocessor Interface Synchronous Read Cycle Specifications Symbol t46 t47 Parameter Data Valid to PCLK with TA_N Low PCLK to DATA 3-State Min 2 2 Max 3 -- Unit tc ns
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Timing Characteristics (continued)
Asynchronous Mode The asynchronous microprocessor interface mode is selected when MPMODE = 0. Interface timing for the asynchronous mode write cycle is given in Figure 26 and in Table 263 below. Interface timing for the read cycle is given in Figure 27 on page 187 and in Table 266 on page 187. In asynchronous mode, the PCLK can be connected to a 77.76 MHz clock. This can be the same source as the D_CLK input when DRPBYP = 0. If DRPBYP is 1, then the D_CLK output can be used. The microprocessor should run at no more than half the frequency of PCLK in asynchronous mode. The timing numbers shown assume a PCLK frequency of 77.76 MHz.
ADDRESS_[15:0] t48 CS_N t48 TS_N t48 DS_N t51 RW_N t52 t49 t50 t49 t49
t53 DATA_[15:0] (INPUT)
t51
t55 HIGH Z t54 t56
t57 HIGH Z
5-9095(F)
TA_N/TEA_N
Figure 26. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0) Table 263. Microprocessor Interface Asynchronous Write Cycle Specifications Symbol tc t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 Parameter PCLK Period ADDRESS Valid to CS_N/DS_N/TS_N Fall TA_N Fall to CS_N/DS_N/TS_N Rise TA_N Fall to DATA/ADDRESS Invalid RW_N Fall to CS_N/DS_N/TS_N Fall DS_N Rise to RW_N Rise DATA Valid to DS_N Fall CS_N/DS_N/TS_N Fall to TA_N/TEA_N High CS_N/DS_N/TS_N Fall to TA_N/TEA_N Fall CS_N/DS_N/TS_N Rise to TA_N/TEA_N Rise CS_N/DS_N/TS_N Rise to TA_N/TEA_N 3-state Min 12.86 0 0 0 0 0 0 4 5 43 42 Max 15 -- -- -- -- -- -- -- 351 54 80 Unit ns1 ns ns ns ns ns ns tc tc ns ns
1. This value represents the timing for a transfer error (TA_N = 1, TEA_N = 0). The typical value during normal access would be 9 tc.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Timing Characteristics (continued)
Table 264. TA_N/TEA_N Cycle Termination for Asynchronous Write Cycle TA_N 0 0 1 1 TEA_N 0 1 0 1 Encoding Description Not possible during asynchronous write cycle. Normal cycle termination. Access to undefined address region--transfer error. No cycle termination--processor generated time-out.
ADDRESS_[15:0] t48 CS_N t48 TS_N t48 DS_N
RW_N
t54 t55 TA_N/TEA_N HIGH Z t58 DATA_[15:0] HIGH Z t56
t57 HIGH Z t59 HIGH Z
5-9096(F)
Figure 27. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0) Table 265. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle TA_N 0 0 1 1 TEA_N 0 1 0 1 Encoding Description Not possible during read cycle. Normal cycle termination. Access to undefined address region--transfer error. No cycle termination--processor generated time-out.
Table 266. Microprocessor Interface Asynchronous Read Cycle Specifications Symbol t58 t59 Parameter TA_N/TEA_N Valid to DATA Valid CS_N/TS_N/DS_N Rise to DATA 3-State Min 13 43 Max 15 56 Unit ns ns
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Timing Characteristics (continued)
Use of a Synchronous Microprocessor with the TSOT0410G4 in Asynchronous Mode The use of a synchronous microprocessor (such as the M860/M8260) to communicate with a TSOT0410G4 configured for asynchronous mode (MPMODE = 0) requires one additional consideration. There is a difference between the operation of a synchronous processor (e.g., M860/M8260) and the asynchronous processors (e.g., 68360). In a synchronous processor, the data is latched on the same edge that detects the assertion of TA_N. In an asynchronous processor, the TA_N (DSACK) signal is detected, and the data is latched one clock period later. In both cases, the TSOT0410G4 meets the timing required by these two different processors. However, a synchronous processor operating with the TSOT0410G4 configured in asynchronous mode will have problems consistently latching the correct data. It will depend on the relationship between the two clocks. As shown in Figure 27 on page 187, the data is presented on the bus 13 ns--15 ns after TA_N is asserted. If the microprocessor has a rising edge within this window, it will capture incorrect data. To operate the TSOT in asynchronous mode with an synchronous processor, add a delay on the TA_N signal from the TSOT0410G4; otherwise, consider using synchronous mode.
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TSOT0410G4 SONET/SDH STS-192 Overhead and Path Processor
Outline Diagram
600-Pin LBGA
Dimensions are in millimeters.
45.00 A1 BALL IDENTIFIER ZONE 41.3/42.3
41.3/42.3
45.00
2.45/3.05
ELECTRICALLY ISOLATED HEAT SPREADER 1.45/1.85 SEATING PLANE 0.20 SOLDER BALL 34 SPACES @ 1.27 = 43.18
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 42 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 531 A C E G B D F H K M P T V Y AB AD AF AH AK AM AP
1.95/2.35 0.60 0.10
A1 BALL CORNER
0.75 0.15
J L N R U W AA AC AE AG AJ AL AN AR
34 SPACES @ 1.27 = 43.18
5-9212.a (F)
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Data Sheet May 2003
Ordering Information
Device Code TSOT0410G14 Package 600-pin LBGA Temperature -40 C to +85 C Comcode 700017424
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. EIA is a registered trademark of The Electronic Industries Association. Motorola is a registered trademark of Motorola, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere Logo are trademarks of Agere Systems Inc.
Copyright (c) 2003 Agere Systems Inc. All Rights Reserved
May 2003 DS02-252SONT-1 (Replaces DS02-252SONT)

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